Info: Starting: Create simulation model
Info: qsys-generate /home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/simulation --family="MAX 10" --part=10M02SCU169C8G
Progress: Loading pokey/int_osc.qsys
Progress: Reading input file
Progress: Adding int_osc_0 [altera_int_osc 18.0]
Progress: Parameterizing module int_osc_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: int_osc: Generating int_osc "int_osc" for SIM_VHDL
Info: int_osc_0: Generating top-level entity altera_int_osc.
Info: int_osc_0: "int_osc" instantiated altera_int_osc "int_osc_0"
Info: int_osc: Done "int_osc" with 2 modules, 3 files
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/int_osc.spd --output-directory=/home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/int_osc.spd --output-directory=/home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/simulation/ directory:
Info: 	mentor/msim_setup.tcl
Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/simulation/ directory:
Info: 	synopsys/vcsmx/synopsys_sim.setup
Info: 	synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in /home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/simulation/ directory:
Info: 	cadence/cds.lib
Info: 	cadence/hdl.var
Info: 	cadence/ncsim_setup.sh
Info: 	1 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/simulation/ directory:
Info: 	aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc --family="MAX 10" --part=10M02SCU169C8G
Progress: Loading pokey/int_osc.qsys
Progress: Reading input file
Progress: Adding int_osc_0 [altera_int_osc 18.0]
Progress: Parameterizing module int_osc_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/branches/eclaireitx/atari_800xl/atari_chips/pokey/int_osc/synthesis --family="MAX 10" --part=10M02SCU169C8G
Progress: Loading pokey/int_osc.qsys
Progress: Reading input file
Progress: Adding int_osc_0 [altera_int_osc 18.0]
Progress: Parameterizing module int_osc_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: int_osc: Generating int_osc "int_osc" for QUARTUS_SYNTH
Info: int_osc_0: Generating top-level entity altera_int_osc.
Info: int_osc_0: "int_osc" instantiated altera_int_osc "int_osc_0"
Info: int_osc: Done "int_osc" with 2 modules, 3 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis