Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash --family="MAX 10" --part=10M04SCU169C8G
Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
Progress: Reading input file
Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
Progress: Parameterizing module onchip_flash_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M04_stereo_covox_auto/flash/synthesis --family="MAX 10" --part=10M04SCU169C8G
Progress: Loading build_10M04_stereo_covox_auto/flash.qsys
Progress: Reading input file
Progress: Adding onchip_flash_0 [altera_onchip_flash 19.1]
Progress: Parameterizing module onchip_flash_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: flash: Generating flash "flash" for QUARTUS_SYNTH
Info: onchip_flash_0: Generating top-level entity altera_onchip_flash
Info: onchip_flash_0: "flash" instantiated altera_onchip_flash "onchip_flash_0"
Info: flash: Done "flash" with 2 modules, 7 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis