Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2 --family="Cyclone V" --part=5CEBA4F23C8
Progress: Loading build_A4EBArom/clkctrl2.qsys
Progress: Reading input file
Progress: Adding altclkctrl_0 [altclkctrl 18.0]
Progress: Parameterizing module altclkctrl_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
: clkctrl2.altclkctrl_0: Targeting device family: Cyclone V.
: clkctrl2.altclkctrl_0: Selecting AUTO allows the compiler to pick the best clock buffer to use, while other values restrict usage to only the given clock buffer.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2/synthesis --family="Cyclone V" --part=5CEBA4F23C8
Progress: Loading build_A4EBArom/clkctrl2.qsys
Progress: Reading input file
Progress: Adding altclkctrl_0 [altclkctrl 18.0]
Progress: Parameterizing module altclkctrl_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
: clkctrl2.altclkctrl_0: Targeting device family: Cyclone V.
: clkctrl2.altclkctrl_0: Selecting AUTO allows the compiler to pick the best clock buffer to use, while other values restrict usage to only the given clock buffer.
Info: clkctrl2: Generating clkctrl2 "clkctrl2" for QUARTUS_SYNTH
Info: altclkctrl_0: Generating top-level entity clkctrl2_altclkctrl_0.
Info: altclkctrl_0: "clkctrl2" instantiated altclkctrl "altclkctrl_0"
Info: clkctrl2: Done "clkctrl2" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis