-- megafunction wizard: %Altera PLL v15.0% -- GENERATION: XML -- pll.vhd -- Generated using ACDS version 15.0 145 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity pll is port ( refclk : in std_logic := '0'; -- refclk.clk rst : in std_logic := '0'; -- reset.reset outclk_0 : out std_logic; -- outclk0.clk outclk_1 : out std_logic; -- outclk1.clk outclk_2 : out std_logic; -- outclk2.clk outclk_3 : out std_logic; -- outclk3.clk locked : out std_logic -- locked.export ); end entity pll; architecture rtl of pll is component pll_0002 is port ( refclk : in std_logic := 'X'; -- clk rst : in std_logic := 'X'; -- reset outclk_0 : out std_logic; -- clk outclk_1 : out std_logic; -- clk outclk_2 : out std_logic; -- clk outclk_3 : out std_logic; -- clk locked : out std_logic -- export ); end component pll_0002; begin pll_inst : component pll_0002 port map ( refclk => refclk, -- refclk.clk rst => rst, -- reset.reset outclk_0 => outclk_0, -- outclk0.clk outclk_1 => outclk_1, -- outclk1.clk outclk_2 => outclk_2, -- outclk2.clk outclk_3 => outclk_3, -- outclk3.clk locked => locked -- locked.export ); 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