diff -ur atari800core_20140301_de1/address_decoder.vhdl atari800core_v1_20140121_mcc216/address_decoder.vhdl --- atari800core_20140301_de1/address_decoder.vhdl 2014-01-20 20:46:50.000000000 +0000 +++ atari800core_v1_20140121_mcc216/address_decoder.vhdl 2014-01-30 21:32:16.000000000 +0000 @@ -10,6 +10,7 @@ use ieee.numeric_std.all; use IEEE.STD_LOGIC_MISC.all; + ENTITY address_decoder IS PORT ( @@ -110,10 +111,12 @@ SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh SDRAM_WRITE_EN : out std_logic; - SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request + --SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request + SDRAM_REQUEST : out std_logic; -- Usual pattern SDRAM_REFRESH : out std_logic; - SDRAM_REPLY : in std_logic; -- This matches the request once complete + --SDRAM_REPLY : in std_logic; -- This matches the request once complete + SDRAM_REQUEST_COMPLETE : in std_logic; SDRAM_DATA : in std_logic_vector(31 downto 0); WRITE_DATA : out std_logic_vector(31 downto 0) @@ -161,12 +164,15 @@ signal ram_chip_select : std_logic; signal sdram_chip_select : std_logic; - signal sdram_request_next : std_logic; - signal sdram_request_reg : std_logic; - signal SDRAM_REQUEST_COMPLETE : std_logic; +-- signal sdram_request_next : std_logic; +-- signal sdram_request_reg : std_logic; +-- signal SDRAM_REQUEST_COMPLETE : std_logic; signal fetch_priority : std_logic_vector(2 downto 0); + signal fetch_wait_next : std_logic_vector(8 downto 0); + signal fetch_wait_reg : std_logic_vector(8 downto 0); + BEGIN -- register process(clk,reset_n) @@ -179,7 +185,8 @@ width_32bit_reg <= '0'; write_enable_reg <= '0'; data_write_reg <= (others=> '0'); - sdram_request_reg <= '0'; + --sdram_request_reg <= '0'; + fetch_wait_reg <= (others=>'0'); elsif (clk'event and clk='1') then addr_reg <= addr_next; state_reg <= state_next; @@ -188,7 +195,8 @@ width_32bit_reg <= width_32bit_next; write_enable_reg <= write_enable_next; data_write_reg <= data_WRITE_next; - sdram_request_reg <= sdram_request_next; + --sdram_request_reg <= sdram_request_next; + fetch_wait_reg <= fetch_wait_next; end if; end process; @@ -211,13 +219,14 @@ -- state machine impl fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH; - process(state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA) + process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA) begin start_request <= '0'; notify_antic <= '0'; notify_cpu <= '0'; notify_zpu <= '0'; state_next <= state_reg; + fetch_wait_next <= std_logic_vector(unsigned(fetch_wait_reg) +1); addr_next <= addr_reg; data_WRITE_next <= data_WRITE_reg; @@ -228,6 +237,7 @@ case state_reg is when state_idle => + fetch_wait_next <= (others=>'0'); write_enable_next <= '0'; width_8bit_next <= '0'; width_16bit_next <= '0'; @@ -300,8 +310,9 @@ RAM_REQUEST <= ram_chip_select; - SDRAM_REQUEST <= sdram_request_next; - SDRAM_REFRESH <= '0'; -- TODO, BROKEN! antic_refresh; + SDRAM_REQUEST <= sdram_chip_select; + --SDRAM_REQUEST <= sdram_request_next; + SDRAM_REFRESH <= fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh; SDRAM_READ_EN <= not(write_enable_next); SDRAM_WRITE_EN <= write_enable_next; @@ -312,8 +323,8 @@ WRITE_DATA <= DATA_WRITE_next; -- a little sdram glue - move to sdram wrapper? TODO - SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request); - sdram_request_next <= sdram_request_reg xor sdram_chip_select; + --SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request); + --sdram_request_next <= sdram_request_reg xor sdram_chip_select; -- Calculate which memory area to use extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu; @@ -466,19 +477,31 @@ X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" => if (portb(7) = '0' and portb(0) = '1') then - request_complete <= ROM_REQUEST_COMPLETE; - MEMORY_DATA(7 downto 0) <= ROM_DATA; - rom_request <= start_request; + --request_complete <= ROM_REQUEST_COMPLETE; + --MEMORY_DATA(7 downto 0) <= ROM_DATA; + --rom_request <= start_request; + MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0); + + if (write_enable_next = '1') then + request_complete <= '1'; + else + request_complete <= sdram_request_COMPLETE; + sdram_chip_select <= start_request; + end if; --ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs) case rom_select is when "00" => ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k + SDRAM_ADDR <="0010000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k when "01" => ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k + SDRAM_ADDR <="0010000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k when "10" => ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k + SDRAM_ADDR <="0010000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k when "11" => ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!) + SDRAM_ADDR <= "0010001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!) end case; else if (use_sdram = '1') then @@ -540,10 +563,19 @@ request_complete <= CART_REQUEST_COMPLETE; else if (portb(1) = '0') then - request_complete <= ROM_REQUEST_COMPLETE; - MEMORY_DATA(7 downto 0) <= ROM_DATA; - rom_request <= start_request; + --request_complete <= ROM_REQUEST_COMPLETE; + --MEMORY_DATA(7 downto 0) <= ROM_DATA; + --rom_request <= start_request; + MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0); + if (write_enable_next = '1') then + request_complete <= '1'; + else + request_complete <= sdram_request_COMPLETE; + sdram_chip_select <= start_request; + end if; + ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k + SDRAM_ADDR <="0010000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k else if (use_sdram = '1') then MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0); @@ -566,18 +598,30 @@ |X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" => if (portb(0) = '1') then - request_complete <= ROM_REQUEST_COMPLETE; - MEMORY_DATA(7 downto 0) <= ROM_DATA; - rom_request <= start_request; + --request_complete <= ROM_REQUEST_COMPLETE; + --MEMORY_DATA(7 downto 0) <= ROM_DATA; + --rom_request <= start_request; + MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0); + if (write_enable_next = '1') then + request_complete <= '1'; + else + request_complete <= sdram_request_COMPLETE; + sdram_chip_select <= start_request; + end if; + case rom_select is when "00" => ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k + SDRAM_ADDR <= "0010000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k when "01" => ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k + SDRAM_ADDR <= "0010000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k when "10" => ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k + SDRAM_ADDR <= "0010000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k when "11" => ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!) + SDRAM_ADDR <= "0010001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!) end case; else diff -ur atari800core_20140301_de1/atari800core.qsf atari800core_v1_20140121_mcc216/atari800core.qsf --- atari800core_20140301_de1/atari800core.qsf 2014-03-01 12:49:08.000000000 +0000 +++ atari800core_v1_20140121_mcc216/atari800core.qsf 2014-02-03 19:39:52.000000000 +0000 @@ -36,8 +36,8 @@ # -------------------------------------------------------------------------- # -set_global_assignment -name FAMILY "Cyclone II" -set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C16E144C8 set_global_assignment -name TOP_LEVEL_ENTITY atari800core set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39 APRIL 11, 2013" @@ -47,504 +47,35 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_location_assignment PIN_A15 -to GPIO_0[4] -set_location_assignment PIN_B15 -to GPIO_0[5] -set_location_assignment PIN_A16 -to GPIO_0[6] -set_location_assignment PIN_B16 -to GPIO_0[7] -set_location_assignment PIN_A17 -to GPIO_0[8] -set_location_assignment PIN_B17 -to GPIO_0[9] -set_location_assignment PIN_A18 -to GPIO_0[10] -set_location_assignment PIN_B18 -to GPIO_0[11] -set_location_assignment PIN_A19 -to GPIO_0[12] -set_location_assignment PIN_B19 -to GPIO_0[13] -set_location_assignment PIN_A20 -to GPIO_0[14] -set_location_assignment PIN_B20 -to GPIO_0[15] -set_location_assignment PIN_C21 -to GPIO_0[16] -set_location_assignment PIN_C22 -to GPIO_0[17] -set_location_assignment PIN_D21 -to GPIO_0[18] -set_location_assignment PIN_D22 -to GPIO_0[19] -set_location_assignment PIN_E21 -to GPIO_0[20] -set_location_assignment PIN_E22 -to GPIO_0[21] -set_location_assignment PIN_F21 -to GPIO_0[22] -set_location_assignment PIN_F22 -to GPIO_0[23] -set_location_assignment PIN_G21 -to GPIO_0[24] -set_location_assignment PIN_G22 -to GPIO_0[25] -set_location_assignment PIN_J21 -to GPIO_0[26] -set_location_assignment PIN_J22 -to GPIO_0[27] -set_location_assignment PIN_K21 -to GPIO_0[28] -set_location_assignment PIN_K22 -to GPIO_0[29] -set_location_assignment PIN_J19 -to GPIO_0[30] -set_location_assignment PIN_J20 -to GPIO_0[31] -set_location_assignment PIN_J18 -to GPIO_0[32] -set_location_assignment PIN_K20 -to GPIO_0[33] -set_location_assignment PIN_L19 -to GPIO_0[34] -set_location_assignment PIN_L18 -to GPIO_0[35] -set_location_assignment PIN_H12 -to GPIO_1[0] -set_location_assignment PIN_H13 -to GPIO_1[1] -set_location_assignment PIN_H14 -to GPIO_1[2] -set_location_assignment PIN_G15 -to GPIO_1[3] -set_location_assignment PIN_E14 -to GPIO_1[4] -set_location_assignment PIN_E15 -to GPIO_1[5] -set_location_assignment PIN_F15 -to GPIO_1[6] -set_location_assignment PIN_G16 -to GPIO_1[7] -set_location_assignment PIN_F12 -to GPIO_1[8] -set_location_assignment PIN_F13 -to GPIO_1[9] -set_location_assignment PIN_C14 -to GPIO_1[10] -set_location_assignment PIN_D14 -to GPIO_1[11] -set_location_assignment PIN_D15 -to GPIO_1[12] -set_location_assignment PIN_D16 -to GPIO_1[13] -set_location_assignment PIN_C17 -to GPIO_1[14] -set_location_assignment PIN_C18 -to GPIO_1[15] -set_location_assignment PIN_C19 -to GPIO_1[16] -set_location_assignment PIN_C20 -to GPIO_1[17] -set_location_assignment PIN_D19 -to GPIO_1[18] -set_location_assignment PIN_D20 -to GPIO_1[19] -set_location_assignment PIN_E20 -to GPIO_1[20] -set_location_assignment PIN_F20 -to GPIO_1[21] -set_location_assignment PIN_E19 -to GPIO_1[22] -set_location_assignment PIN_E18 -to GPIO_1[23] -set_location_assignment PIN_G20 -to GPIO_1[24] -set_location_assignment PIN_G18 -to GPIO_1[25] -set_location_assignment PIN_G17 -to GPIO_1[26] -set_location_assignment PIN_H17 -to GPIO_1[27] -set_location_assignment PIN_J15 -to GPIO_1[28] -set_location_assignment PIN_H18 -to GPIO_1[29] -set_location_assignment PIN_N22 -to GPIO_1[30] -set_location_assignment PIN_N21 -to GPIO_1[31] -set_location_assignment PIN_P15 -to GPIO_1[32] -set_location_assignment PIN_N15 -to GPIO_1[33] -set_location_assignment PIN_P17 -to GPIO_1[34] -set_location_assignment PIN_P18 -to GPIO_1[35] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35] -set_location_assignment PIN_L22 -to SW[0] -set_location_assignment PIN_L21 -to SW[1] -set_location_assignment PIN_M22 -to SW[2] -set_location_assignment PIN_V12 -to SW[3] -set_location_assignment PIN_W12 -to SW[4] -set_location_assignment PIN_U12 -to SW[5] -set_location_assignment PIN_U11 -to SW[6] -set_location_assignment PIN_M2 -to SW[7] -set_location_assignment PIN_M1 -to SW[8] -set_location_assignment PIN_L2 -to SW[9] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[0] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[1] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[2] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[3] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[4] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[5] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[6] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[7] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[8] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[9] -set_location_assignment PIN_J2 -to HEX0[0] -set_location_assignment PIN_J1 -to HEX0[1] -set_location_assignment PIN_H2 -to HEX0[2] -set_location_assignment PIN_H1 -to HEX0[3] -set_location_assignment PIN_F2 -to HEX0[4] -set_location_assignment PIN_F1 -to HEX0[5] -set_location_assignment PIN_E2 -to HEX0[6] -set_location_assignment PIN_E1 -to HEX1[0] -set_location_assignment PIN_H6 -to HEX1[1] -set_location_assignment PIN_H5 -to HEX1[2] -set_location_assignment PIN_H4 -to HEX1[3] -set_location_assignment PIN_G3 -to HEX1[4] -set_location_assignment PIN_D2 -to HEX1[5] -set_location_assignment PIN_D1 -to HEX1[6] -set_location_assignment PIN_G5 -to HEX2[0] -set_location_assignment PIN_G6 -to HEX2[1] -set_location_assignment PIN_C2 -to HEX2[2] -set_location_assignment PIN_C1 -to HEX2[3] -set_location_assignment PIN_E3 -to HEX2[4] -set_location_assignment PIN_E4 -to HEX2[5] -set_location_assignment PIN_D3 -to HEX2[6] -set_location_assignment PIN_F4 -to HEX3[0] -set_location_assignment PIN_D5 -to HEX3[1] -set_location_assignment PIN_D6 -to HEX3[2] -set_location_assignment PIN_J4 -to HEX3[3] -set_location_assignment PIN_L8 -to HEX3[4] -set_location_assignment PIN_F3 -to HEX3[5] -set_location_assignment PIN_D4 -to HEX3[6] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6] -set_location_assignment PIN_R22 -to KEY[0] -set_location_assignment PIN_R21 -to KEY[1] -set_location_assignment PIN_T22 -to KEY[2] -set_location_assignment PIN_T21 -to KEY[3] -set_location_assignment PIN_R20 -to LEDR[0] -set_location_assignment PIN_R19 -to LEDR[1] -set_location_assignment PIN_U19 -to LEDR[2] -set_location_assignment PIN_Y19 -to LEDR[3] -set_location_assignment PIN_T18 -to LEDR[4] -set_location_assignment PIN_V19 -to LEDR[5] -set_location_assignment PIN_Y18 -to LEDR[6] -set_location_assignment PIN_U18 -to LEDR[7] -set_location_assignment PIN_R18 -to LEDR[8] -set_location_assignment PIN_R17 -to LEDR[9] -set_location_assignment PIN_U22 -to LEDG[0] -set_location_assignment PIN_U21 -to LEDG[1] -set_location_assignment PIN_V22 -to LEDG[2] -set_location_assignment PIN_V21 -to LEDG[3] -set_location_assignment PIN_W22 -to LEDG[4] -set_location_assignment PIN_W21 -to LEDG[5] -set_location_assignment PIN_Y22 -to LEDG[6] -set_location_assignment PIN_Y21 -to LEDG[7] -set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0] -set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1] -set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2] -set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7] -set_location_assignment PIN_D12 -to CLOCK_27[0] -set_location_assignment PIN_E12 -to CLOCK_27[1] -set_location_assignment PIN_B12 -to CLOCK_24[0] -set_location_assignment PIN_A12 -to CLOCK_24[1] -set_location_assignment PIN_L1 -to CLOCK_50 -set_location_assignment PIN_M21 -to EXT_CLOCK -set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1] -set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0] -set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1] -set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50 -set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK -set_location_assignment PIN_H15 -to PS2_CLK -set_location_assignment PIN_J14 -to PS2_DAT -set_location_assignment PIN_F14 -to UART_RXD -set_location_assignment PIN_G12 -to UART_TXD -set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK -set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT -set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD -set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD -set_location_assignment PIN_E8 -to TDI -set_location_assignment PIN_D8 -to TCS -set_location_assignment PIN_C7 -to TCK -set_location_assignment PIN_D7 -to TDO -set_instance_assignment -name IO_STANDARD LVTTL -to TDI -set_instance_assignment -name IO_STANDARD LVTTL -to TCS -set_instance_assignment -name IO_STANDARD LVTTL -to TCK -set_instance_assignment -name IO_STANDARD LVTTL -to TDO -set_location_assignment PIN_D9 -to VGA_R[0] -set_location_assignment PIN_C9 -to VGA_R[1] -set_location_assignment PIN_A7 -to VGA_R[2] -set_location_assignment PIN_B7 -to VGA_R[3] -set_location_assignment PIN_B8 -to VGA_G[0] -set_location_assignment PIN_C10 -to VGA_G[1] -set_location_assignment PIN_B9 -to VGA_G[2] -set_location_assignment PIN_A8 -to VGA_G[3] -set_location_assignment PIN_A9 -to VGA_B[0] -set_location_assignment PIN_D11 -to VGA_B[1] -set_location_assignment PIN_A10 -to VGA_B[2] -set_location_assignment PIN_B10 -to VGA_B[3] -set_location_assignment PIN_A11 -to VGA_HS -set_location_assignment PIN_B11 -to VGA_VS -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS -set_location_assignment PIN_A3 -to I2C_SCLK -set_location_assignment PIN_B3 -to I2C_SDAT -set_location_assignment PIN_A6 -to AUD_ADCLRCK -set_location_assignment PIN_B6 -to AUD_ADCDAT -set_location_assignment PIN_A5 -to AUD_DACLRCK -set_location_assignment PIN_B5 -to AUD_DACDAT -set_location_assignment PIN_B4 -to AUD_XCK -set_location_assignment PIN_A4 -to AUD_BCLK -set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK -set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK -set_location_assignment PIN_W4 -to DRAM_ADDR[0] -set_location_assignment PIN_W5 -to DRAM_ADDR[1] -set_location_assignment PIN_Y3 -to DRAM_ADDR[2] -set_location_assignment PIN_Y4 -to DRAM_ADDR[3] -set_location_assignment PIN_R6 -to DRAM_ADDR[4] -set_location_assignment PIN_R5 -to DRAM_ADDR[5] -set_location_assignment PIN_P6 -to DRAM_ADDR[6] -set_location_assignment PIN_P5 -to DRAM_ADDR[7] -set_location_assignment PIN_P3 -to DRAM_ADDR[8] -set_location_assignment PIN_N4 -to DRAM_ADDR[9] -set_location_assignment PIN_W3 -to DRAM_ADDR[10] -set_location_assignment PIN_N6 -to DRAM_ADDR[11] -set_location_assignment PIN_U3 -to DRAM_BA_0 -set_location_assignment PIN_V4 -to DRAM_BA_1 -set_location_assignment PIN_T3 -to DRAM_CAS_N -set_location_assignment PIN_N3 -to DRAM_CKE -set_location_assignment PIN_U4 -to DRAM_CLK -set_location_assignment PIN_T6 -to DRAM_CS_N -set_location_assignment PIN_U1 -to DRAM_DQ[0] -set_location_assignment PIN_U2 -to DRAM_DQ[1] -set_location_assignment PIN_V1 -to DRAM_DQ[2] -set_location_assignment PIN_V2 -to DRAM_DQ[3] -set_location_assignment PIN_W1 -to DRAM_DQ[4] -set_location_assignment PIN_W2 -to DRAM_DQ[5] -set_location_assignment PIN_Y1 -to DRAM_DQ[6] -set_location_assignment PIN_Y2 -to DRAM_DQ[7] -set_location_assignment PIN_N1 -to DRAM_DQ[8] -set_location_assignment PIN_N2 -to DRAM_DQ[9] -set_location_assignment PIN_P1 -to DRAM_DQ[10] -set_location_assignment PIN_P2 -to DRAM_DQ[11] -set_location_assignment PIN_R1 -to DRAM_DQ[12] -set_location_assignment PIN_R2 -to DRAM_DQ[13] -set_location_assignment PIN_T1 -to DRAM_DQ[14] -set_location_assignment PIN_T2 -to DRAM_DQ[15] -set_location_assignment PIN_R7 -to DRAM_LDQM -set_location_assignment PIN_T5 -to DRAM_RAS_N -set_location_assignment PIN_M5 -to DRAM_UDQM -set_location_assignment PIN_R8 -to DRAM_WE_N -set_location_assignment PIN_AB20 -to FL_ADDR[0] -set_location_assignment PIN_AA14 -to FL_ADDR[1] -set_location_assignment PIN_Y16 -to FL_ADDR[2] -set_location_assignment PIN_R15 -to FL_ADDR[3] -set_location_assignment PIN_T15 -to FL_ADDR[4] -set_location_assignment PIN_U15 -to FL_ADDR[5] -set_location_assignment PIN_V15 -to FL_ADDR[6] -set_location_assignment PIN_W15 -to FL_ADDR[7] -set_location_assignment PIN_R14 -to FL_ADDR[8] -set_location_assignment PIN_Y13 -to FL_ADDR[9] -set_location_assignment PIN_R12 -to FL_ADDR[10] -set_location_assignment PIN_T12 -to FL_ADDR[11] -set_location_assignment PIN_AB14 -to FL_ADDR[12] -set_location_assignment PIN_AA13 -to FL_ADDR[13] -set_location_assignment PIN_AB13 -to FL_ADDR[14] -set_location_assignment PIN_AA12 -to FL_ADDR[15] -set_location_assignment PIN_AB12 -to FL_ADDR[16] -set_location_assignment PIN_AA20 -to FL_ADDR[17] -set_location_assignment PIN_U14 -to FL_ADDR[18] -set_location_assignment PIN_V14 -to FL_ADDR[19] -set_location_assignment PIN_U13 -to FL_ADDR[20] -set_location_assignment PIN_R13 -to FL_ADDR[21] -set_location_assignment PIN_AB16 -to FL_DQ[0] -set_location_assignment PIN_AA16 -to FL_DQ[1] -set_location_assignment PIN_AB17 -to FL_DQ[2] -set_location_assignment PIN_AA17 -to FL_DQ[3] -set_location_assignment PIN_AB18 -to FL_DQ[4] -set_location_assignment PIN_AA18 -to FL_DQ[5] -set_location_assignment PIN_AB19 -to FL_DQ[6] -set_location_assignment PIN_AA19 -to FL_DQ[7] -set_location_assignment PIN_AA15 -to FL_OE_N -set_location_assignment PIN_W14 -to FL_RST_N -set_location_assignment PIN_Y14 -to FL_WE_N -set_location_assignment PIN_AA3 -to SRAM_ADDR[0] -set_location_assignment PIN_AB3 -to SRAM_ADDR[1] -set_location_assignment PIN_AA4 -to SRAM_ADDR[2] -set_location_assignment PIN_AB4 -to SRAM_ADDR[3] -set_location_assignment PIN_AA5 -to SRAM_ADDR[4] -set_location_assignment PIN_AB10 -to SRAM_ADDR[5] -set_location_assignment PIN_AA11 -to SRAM_ADDR[6] -set_location_assignment PIN_AB11 -to SRAM_ADDR[7] -set_location_assignment PIN_V11 -to SRAM_ADDR[8] -set_location_assignment PIN_W11 -to SRAM_ADDR[9] -set_location_assignment PIN_R11 -to SRAM_ADDR[10] -set_location_assignment PIN_T11 -to SRAM_ADDR[11] -set_location_assignment PIN_Y10 -to SRAM_ADDR[12] -set_location_assignment PIN_U10 -to SRAM_ADDR[13] -set_location_assignment PIN_R10 -to SRAM_ADDR[14] -set_location_assignment PIN_T7 -to SRAM_ADDR[15] -set_location_assignment PIN_Y6 -to SRAM_ADDR[16] -set_location_assignment PIN_Y5 -to SRAM_ADDR[17] -set_location_assignment PIN_AB5 -to SRAM_CE_N -set_location_assignment PIN_AA6 -to SRAM_DQ[0] -set_location_assignment PIN_AB6 -to SRAM_DQ[1] -set_location_assignment PIN_AA7 -to SRAM_DQ[2] -set_location_assignment PIN_AB7 -to SRAM_DQ[3] -set_location_assignment PIN_AA8 -to SRAM_DQ[4] -set_location_assignment PIN_AB8 -to SRAM_DQ[5] -set_location_assignment PIN_AA9 -to SRAM_DQ[6] -set_location_assignment PIN_AB9 -to SRAM_DQ[7] -set_location_assignment PIN_Y9 -to SRAM_DQ[8] -set_location_assignment PIN_W9 -to SRAM_DQ[9] -set_location_assignment PIN_V9 -to SRAM_DQ[10] -set_location_assignment PIN_U9 -to SRAM_DQ[11] -set_location_assignment PIN_R9 -to SRAM_DQ[12] -set_location_assignment PIN_W8 -to SRAM_DQ[13] -set_location_assignment PIN_V8 -to SRAM_DQ[14] -set_location_assignment PIN_U8 -to SRAM_DQ[15] -set_location_assignment PIN_Y7 -to SRAM_LB_N -set_location_assignment PIN_T8 -to SRAM_OE_N -set_location_assignment PIN_W7 -to SRAM_UB_N -set_location_assignment PIN_AA10 -to SRAM_WE_N -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_CE_N -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_LB_N -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_OE_N -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_UB_N -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_WE_N -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[0] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[1] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[2] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[3] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[4] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[5] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[6] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[7] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[8] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[9] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[10] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[11] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[12] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[13] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[14] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[15] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[16] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[17] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[0] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[1] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[2] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[3] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[4] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[5] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[6] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[7] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[8] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[9] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[10] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[11] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[12] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[13] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[14] -set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[15] -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_134 -to VGA_R[1] +set_location_assignment PIN_133 -to VGA_R[2] +set_location_assignment PIN_132 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_G[0] +set_location_assignment PIN_142 -to VGA_G[1] +set_location_assignment PIN_143 -to VGA_G[2] +set_location_assignment PIN_144 -to VGA_G[3] +set_location_assignment PIN_4 -to VGA_B[0] +set_location_assignment PIN_7 -to VGA_B[1] +set_location_assignment PIN_10 -to VGA_B[2] +set_location_assignment PIN_11 -to VGA_B[3] +set_location_assignment PIN_136 -to VGA_HS +set_location_assignment PIN_137 -to VGA_VS set_global_assignment -name ENABLE_SIGNALTAP ON -set_location_assignment PIN_V20 -to SD_CLK -set_location_assignment PIN_Y20 -to SD_CMD -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_location_assignment PIN_44 -to SD_CLK +set_location_assignment PIN_46 -to SD_CMD set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF set_global_assignment -name BLOCK_DESIGN_NAMING AUTO set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_location_assignment PIN_W20 -to SD_DATA -set_location_assignment PIN_U20 -to SD_THREE -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED @@ -555,6 +86,215 @@ set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" + +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp +set_location_assignment PIN_28 -to AUDIO_L +set_location_assignment PIN_30 -to AUDIO_R +set_location_assignment PIN_53 -to CPU_RESET_n +set_location_assignment PIN_55 -to FPGA_CLK +set_location_assignment PIN_127 -to JOY1_n[0] +set_location_assignment PIN_91 -to JOY1_n[1] +set_location_assignment PIN_90 -to JOY1_n[2] +set_location_assignment PIN_88 -to JOY1_n[3] +set_location_assignment PIN_89 -to JOY1_n[4] +set_location_assignment PIN_126 -to JOY1_n[5] +set_location_assignment PIN_128 -to JOY2_n[0] +set_location_assignment PIN_25 -to JOY2_n[1] +set_location_assignment PIN_24 -to JOY2_n[2] +set_location_assignment PIN_22 -to JOY2_n[3] +set_location_assignment PIN_23 -to JOY2_n[4] +set_location_assignment PIN_129 -to JOY2_n[5] +set_location_assignment PIN_33 -to PS2K_DAT +set_location_assignment PIN_39 -to PS2K_CLK +set_location_assignment PIN_32 -to PS2M_DAT +set_location_assignment PIN_31 -to PS2M_CLK +set_location_assignment PIN_52 -to SD_DAT0 +set_location_assignment PIN_49 -to SD_DAT3 +set_location_assignment PIN_42 -to USB_P +set_location_assignment PIN_43 -to USB_N +set_location_assignment PIN_50 -to USB2_P +set_location_assignment PIN_51 -to USB2_N +set_location_assignment PIN_112 -to SDRAM_CLK +set_location_assignment PIN_61 -to SDRAM_A[0] +set_location_assignment PIN_60 -to SDRAM_A[1] +set_location_assignment PIN_59 -to SDRAM_A[2] +set_location_assignment PIN_58 -to SDRAM_A[3] +set_location_assignment PIN_125 -to SDRAM_A[4] +set_location_assignment PIN_121 -to SDRAM_A[5] +set_location_assignment PIN_120 -to SDRAM_A[6] +set_location_assignment PIN_119 -to SDRAM_A[7] +set_location_assignment PIN_115 -to SDRAM_A[8] +set_location_assignment PIN_114 -to SDRAM_A[9] +set_location_assignment PIN_64 -to SDRAM_A[10] +set_location_assignment PIN_113 -to SDRAM_A[11] +set_location_assignment PIN_111 -to SDRAM_A[12] +set_location_assignment PIN_66 -to SDRAM_BA[0] +set_location_assignment PIN_65 -to SDRAM_BA[1] +set_location_assignment PIN_87 -to SDRAM_DQ[0] +set_location_assignment PIN_86 -to SDRAM_DQ[1] +set_location_assignment PIN_85 -to SDRAM_DQ[2] +set_location_assignment PIN_83 -to SDRAM_DQ[3] +set_location_assignment PIN_80 -to SDRAM_DQ[4] +set_location_assignment PIN_79 -to SDRAM_DQ[5] +set_location_assignment PIN_77 -to SDRAM_DQ[6] +set_location_assignment PIN_76 -to SDRAM_DQ[7] +set_location_assignment PIN_106 -to SDRAM_DQ[8] +set_location_assignment PIN_105 -to SDRAM_DQ[9] +set_location_assignment PIN_104 -to SDRAM_DQ[10] +set_location_assignment PIN_103 -to SDRAM_DQ[11] +set_location_assignment PIN_101 -to SDRAM_DQ[12] +set_location_assignment PIN_100 -to SDRAM_DQ[13] +set_location_assignment PIN_99 -to SDRAM_DQ[14] +set_location_assignment PIN_98 -to SDRAM_DQ[15] +set_location_assignment PIN_67 -to SDRAM_CS_n +set_location_assignment PIN_68 -to SDRAM_RAS_n +set_location_assignment PIN_69 -to SDRAM_CAS_n +set_location_assignment PIN_71 -to SDRAM_WE_n +set_location_assignment PIN_6 -to CFG_DOUT +set_location_assignment PIN_8 -to CFG_CS_n +set_location_assignment PIN_12 -to CFG_CLK +set_location_assignment PIN_13 -to CFG_DIN +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_location_assignment PIN_72 -to SDRAM_DQM_n[0] +set_location_assignment PIN_110 -to SDRAM_DQM_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_R +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPU_RESET_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT0 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_P +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_P +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_n +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_n +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_n +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CS_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DIN +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DOUT +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT +set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0] +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n +set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3] + + +set_global_assignment -name VERILOG_FILE hq_dac.v +set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v +set_global_assignment -name VHDL_FILE romlo.vhd +set_global_assignment -name VHDL_FILE romhi.vhd +set_global_assignment -name VHDL_FILE ramint.vhd set_global_assignment -name VHDL_FILE atari800core.vhd set_global_assignment -name VHDL_FILE spi_master.vhd set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl @@ -565,19 +305,12 @@ set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd -set_global_assignment -name VHDL_FILE i2s_intf.vhd -set_global_assignment -name VHDL_FILE i2c_loader.vhd set_global_assignment -name VHDL_FILE cpu.vhd -set_global_assignment -name VHDL_FILE ledsw.vhd -set_global_assignment -name VHDL_FILE hexdecoder.vhd set_global_assignment -name QIP_FILE pll.qip set_global_assignment -name SDC_FILE atari800core.sdc -set_global_assignment -name VHDL_FILE dumprom.vhdl set_global_assignment -name VHDL_FILE reg_file.vhdl set_global_assignment -name VHDL_FILE address_decoder.vhdl -set_global_assignment -name VHDL_FILE i2sslave.vhdl set_global_assignment -name VHDL_FILE pokey.vhdl -set_global_assignment -name VHDL_FILE nmigen.vhdl set_global_assignment -name VHDL_FILE enable_divider.vhdl set_global_assignment -name VHDL_FILE poly_17_9.vhdl set_global_assignment -name VHDL_FILE poly_5.vhdl @@ -587,11 +320,8 @@ set_global_assignment -name VHDL_FILE pokey_mixer.vhdl set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl -set_global_assignment -name VHDL_FILE tvsync.vhdl set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl -set_global_assignment -name VHDL_FILE flashrom.vhdl -set_global_assignment -name VHDL_FILE sram.vhdl set_global_assignment -name VHDL_FILE antic.vhdl set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl set_global_assignment -name VHDL_FILE antic_counter.vhdl @@ -608,19 +338,11 @@ set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd set_global_assignment -name VHDL_FILE wide_delay_line.vhdl set_global_assignment -name VHDL_FILE irq_glue.vhdl -set_global_assignment -name VHDL_FILE gpio.vhd set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl set_global_assignment -name VHDL_FILE zpu_glue.vhdl set_global_assignment -name QIP_FILE zpu_ram.qip set_global_assignment -name QIP_FILE zpu_rom.qip -set_location_assignment PIN_A13 -to GPIO_0[0] -set_location_assignment PIN_B13 -to GPIO_0[1] -set_location_assignment PIN_A14 -to GPIO_0[2] -set_location_assignment PIN_B14 -to GPIO_0[3] - -set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp - - - +set_global_assignment -name VHDL_FILE internalromram.vhd +set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff -ur atari800core_20140301_de1/atari800core.qsf~ atari800core_v1_20140121_mcc216/atari800core.qsf~ --- atari800core_20140301_de1/atari800core.qsf~ 2014-03-01 12:42:20.000000000 +0000 +++ atari800core_v1_20140121_mcc216/atari800core.qsf~ 2014-01-26 10:34:19.000000000 +0000 @@ -36,8 +36,8 @@ # -------------------------------------------------------------------------- # -set_global_assignment -name FAMILY "Cyclone II" -set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C16E144C8 set_global_assignment -name TOP_LEVEL_ENTITY atari800core set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39 APRIL 11, 2013" @@ -47,465 +47,36 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_location_assignment PIN_A15 -to GPIO_0[4] -set_location_assignment PIN_B15 -to GPIO_0[5] -set_location_assignment PIN_A16 -to GPIO_0[6] -set_location_assignment PIN_B16 -to GPIO_0[7] -set_location_assignment PIN_A17 -to GPIO_0[8] -set_location_assignment PIN_B17 -to GPIO_0[9] -set_location_assignment PIN_A18 -to GPIO_0[10] -set_location_assignment PIN_B18 -to GPIO_0[11] -set_location_assignment PIN_A19 -to GPIO_0[12] -set_location_assignment PIN_B19 -to GPIO_0[13] -set_location_assignment PIN_A20 -to GPIO_0[14] -set_location_assignment PIN_B20 -to GPIO_0[15] -set_location_assignment PIN_C21 -to GPIO_0[16] -set_location_assignment PIN_C22 -to GPIO_0[17] -set_location_assignment PIN_D21 -to GPIO_0[18] -set_location_assignment PIN_D22 -to GPIO_0[19] -set_location_assignment PIN_E21 -to GPIO_0[20] -set_location_assignment PIN_E22 -to GPIO_0[21] -set_location_assignment PIN_F21 -to GPIO_0[22] -set_location_assignment PIN_F22 -to GPIO_0[23] -set_location_assignment PIN_G21 -to GPIO_0[24] -set_location_assignment PIN_G22 -to GPIO_0[25] -set_location_assignment PIN_J21 -to GPIO_0[26] -set_location_assignment PIN_J22 -to GPIO_0[27] -set_location_assignment PIN_K21 -to GPIO_0[28] -set_location_assignment PIN_K22 -to GPIO_0[29] -set_location_assignment PIN_J19 -to GPIO_0[30] -set_location_assignment PIN_J20 -to GPIO_0[31] -set_location_assignment PIN_J18 -to GPIO_0[32] -set_location_assignment PIN_K20 -to GPIO_0[33] -set_location_assignment PIN_L19 -to GPIO_0[34] -set_location_assignment PIN_L18 -to GPIO_0[35] -set_location_assignment PIN_H12 -to GPIO_1[0] -set_location_assignment PIN_H13 -to GPIO_1[1] -set_location_assignment PIN_H14 -to GPIO_1[2] -set_location_assignment PIN_G15 -to GPIO_1[3] -set_location_assignment PIN_E14 -to GPIO_1[4] -set_location_assignment PIN_E15 -to GPIO_1[5] -set_location_assignment PIN_F15 -to GPIO_1[6] -set_location_assignment PIN_G16 -to GPIO_1[7] -set_location_assignment PIN_F12 -to GPIO_1[8] -set_location_assignment PIN_F13 -to GPIO_1[9] -set_location_assignment PIN_C14 -to GPIO_1[10] -set_location_assignment PIN_D14 -to GPIO_1[11] -set_location_assignment PIN_D15 -to GPIO_1[12] -set_location_assignment PIN_D16 -to GPIO_1[13] -set_location_assignment PIN_C17 -to GPIO_1[14] -set_location_assignment PIN_C18 -to GPIO_1[15] -set_location_assignment PIN_C19 -to GPIO_1[16] -set_location_assignment PIN_C20 -to GPIO_1[17] -set_location_assignment PIN_D19 -to GPIO_1[18] -set_location_assignment PIN_D20 -to GPIO_1[19] -set_location_assignment PIN_E20 -to GPIO_1[20] -set_location_assignment PIN_F20 -to GPIO_1[21] -set_location_assignment PIN_E19 -to GPIO_1[22] -set_location_assignment PIN_E18 -to GPIO_1[23] -set_location_assignment PIN_G20 -to GPIO_1[24] -set_location_assignment PIN_G18 -to GPIO_1[25] -set_location_assignment PIN_G17 -to GPIO_1[26] -set_location_assignment PIN_H17 -to GPIO_1[27] -set_location_assignment PIN_J15 -to GPIO_1[28] -set_location_assignment PIN_H18 -to GPIO_1[29] -set_location_assignment PIN_N22 -to GPIO_1[30] -set_location_assignment PIN_N21 -to GPIO_1[31] -set_location_assignment PIN_P15 -to GPIO_1[32] -set_location_assignment PIN_N15 -to GPIO_1[33] -set_location_assignment PIN_P17 -to GPIO_1[34] -set_location_assignment PIN_P18 -to GPIO_1[35] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34] -set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35] -set_location_assignment PIN_L22 -to SW[0] -set_location_assignment PIN_L21 -to SW[1] -set_location_assignment PIN_M22 -to SW[2] -set_location_assignment PIN_V12 -to SW[3] -set_location_assignment PIN_W12 -to SW[4] -set_location_assignment PIN_U12 -to SW[5] -set_location_assignment PIN_U11 -to SW[6] -set_location_assignment PIN_M2 -to SW[7] -set_location_assignment PIN_M1 -to SW[8] -set_location_assignment PIN_L2 -to SW[9] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[0] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[1] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[2] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[3] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[4] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[5] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[6] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[7] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[8] -set_instance_assignment -name IO_STANDARD LVTTL -to SW[9] -set_location_assignment PIN_J2 -to HEX0[0] -set_location_assignment PIN_J1 -to HEX0[1] -set_location_assignment PIN_H2 -to HEX0[2] -set_location_assignment PIN_H1 -to HEX0[3] -set_location_assignment PIN_F2 -to HEX0[4] -set_location_assignment PIN_F1 -to HEX0[5] -set_location_assignment PIN_E2 -to HEX0[6] -set_location_assignment PIN_E1 -to HEX1[0] -set_location_assignment PIN_H6 -to HEX1[1] -set_location_assignment PIN_H5 -to HEX1[2] -set_location_assignment PIN_H4 -to HEX1[3] -set_location_assignment PIN_G3 -to HEX1[4] -set_location_assignment PIN_D2 -to HEX1[5] -set_location_assignment PIN_D1 -to HEX1[6] -set_location_assignment PIN_G5 -to HEX2[0] -set_location_assignment PIN_G6 -to HEX2[1] -set_location_assignment PIN_C2 -to HEX2[2] -set_location_assignment PIN_C1 -to HEX2[3] -set_location_assignment PIN_E3 -to HEX2[4] -set_location_assignment PIN_E4 -to HEX2[5] -set_location_assignment PIN_D3 -to HEX2[6] -set_location_assignment PIN_F4 -to HEX3[0] -set_location_assignment PIN_D5 -to HEX3[1] -set_location_assignment PIN_D6 -to HEX3[2] -set_location_assignment PIN_J4 -to HEX3[3] -set_location_assignment PIN_L8 -to HEX3[4] -set_location_assignment PIN_F3 -to HEX3[5] -set_location_assignment PIN_D4 -to HEX3[6] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5] -set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6] -set_location_assignment PIN_R22 -to KEY[0] -set_location_assignment PIN_R21 -to KEY[1] -set_location_assignment PIN_T22 -to KEY[2] -set_location_assignment PIN_T21 -to KEY[3] -set_location_assignment PIN_R20 -to LEDR[0] -set_location_assignment PIN_R19 -to LEDR[1] -set_location_assignment PIN_U19 -to LEDR[2] -set_location_assignment PIN_Y19 -to LEDR[3] -set_location_assignment PIN_T18 -to LEDR[4] -set_location_assignment PIN_V19 -to LEDR[5] -set_location_assignment PIN_Y18 -to LEDR[6] -set_location_assignment PIN_U18 -to LEDR[7] -set_location_assignment PIN_R18 -to LEDR[8] -set_location_assignment PIN_R17 -to LEDR[9] -set_location_assignment PIN_U22 -to LEDG[0] -set_location_assignment PIN_U21 -to LEDG[1] -set_location_assignment PIN_V22 -to LEDG[2] -set_location_assignment PIN_V21 -to LEDG[3] -set_location_assignment PIN_W22 -to LEDG[4] -set_location_assignment PIN_W21 -to LEDG[5] -set_location_assignment PIN_Y22 -to LEDG[6] -set_location_assignment PIN_Y21 -to LEDG[7] -set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0] -set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1] -set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2] -set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6] -set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7] -set_location_assignment PIN_D12 -to CLOCK_27[0] -set_location_assignment PIN_E12 -to CLOCK_27[1] -set_location_assignment PIN_B12 -to CLOCK_24[0] -set_location_assignment PIN_A12 -to CLOCK_24[1] -set_location_assignment PIN_L1 -to CLOCK_50 -set_location_assignment PIN_M21 -to EXT_CLOCK -set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1] -set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0] -set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1] -set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50 -set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK -set_location_assignment PIN_H15 -to PS2_CLK -set_location_assignment PIN_J14 -to PS2_DAT -set_location_assignment PIN_F14 -to UART_RXD -set_location_assignment PIN_G12 -to UART_TXD -set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK -set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT -set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD -set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD -set_location_assignment PIN_E8 -to TDI -set_location_assignment PIN_D8 -to TCS -set_location_assignment PIN_C7 -to TCK -set_location_assignment PIN_D7 -to TDO -set_instance_assignment -name IO_STANDARD LVTTL -to TDI -set_instance_assignment -name IO_STANDARD LVTTL -to TCS -set_instance_assignment -name IO_STANDARD LVTTL -to TCK -set_instance_assignment -name IO_STANDARD LVTTL -to TDO -set_location_assignment PIN_D9 -to VGA_R[0] -set_location_assignment PIN_C9 -to VGA_R[1] -set_location_assignment PIN_A7 -to VGA_R[2] -set_location_assignment PIN_B7 -to VGA_R[3] -set_location_assignment PIN_B8 -to VGA_G[0] -set_location_assignment PIN_C10 -to VGA_G[1] -set_location_assignment PIN_B9 -to VGA_G[2] -set_location_assignment PIN_A8 -to VGA_G[3] -set_location_assignment PIN_A9 -to VGA_B[0] -set_location_assignment PIN_D11 -to VGA_B[1] -set_location_assignment PIN_A10 -to VGA_B[2] -set_location_assignment PIN_B10 -to VGA_B[3] -set_location_assignment PIN_A11 -to VGA_HS -set_location_assignment PIN_B11 -to VGA_VS -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3] -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS -set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS -set_location_assignment PIN_A3 -to I2C_SCLK -set_location_assignment PIN_B3 -to I2C_SDAT -set_location_assignment PIN_A6 -to AUD_ADCLRCK -set_location_assignment PIN_B6 -to AUD_ADCDAT -set_location_assignment PIN_A5 -to AUD_DACLRCK -set_location_assignment PIN_B5 -to AUD_DACDAT -set_location_assignment PIN_B4 -to AUD_XCK -set_location_assignment PIN_A4 -to AUD_BCLK -set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK -set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK -set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK -set_location_assignment PIN_W4 -to DRAM_ADDR[0] -set_location_assignment PIN_W5 -to DRAM_ADDR[1] -set_location_assignment PIN_Y3 -to DRAM_ADDR[2] -set_location_assignment PIN_Y4 -to DRAM_ADDR[3] -set_location_assignment PIN_R6 -to DRAM_ADDR[4] -set_location_assignment PIN_R5 -to DRAM_ADDR[5] -set_location_assignment PIN_P6 -to DRAM_ADDR[6] -set_location_assignment PIN_P5 -to DRAM_ADDR[7] -set_location_assignment PIN_P3 -to DRAM_ADDR[8] -set_location_assignment PIN_N4 -to DRAM_ADDR[9] -set_location_assignment PIN_W3 -to DRAM_ADDR[10] -set_location_assignment PIN_N6 -to DRAM_ADDR[11] -set_location_assignment PIN_U3 -to DRAM_BA_0 -set_location_assignment PIN_V4 -to DRAM_BA_1 -set_location_assignment PIN_T3 -to DRAM_CAS_N -set_location_assignment PIN_N3 -to DRAM_CKE -set_location_assignment PIN_U4 -to DRAM_CLK -set_location_assignment PIN_T6 -to DRAM_CS_N -set_location_assignment PIN_U1 -to DRAM_DQ[0] -set_location_assignment PIN_U2 -to DRAM_DQ[1] -set_location_assignment PIN_V1 -to DRAM_DQ[2] -set_location_assignment PIN_V2 -to DRAM_DQ[3] -set_location_assignment PIN_W1 -to DRAM_DQ[4] -set_location_assignment PIN_W2 -to DRAM_DQ[5] -set_location_assignment PIN_Y1 -to DRAM_DQ[6] -set_location_assignment PIN_Y2 -to DRAM_DQ[7] -set_location_assignment PIN_N1 -to DRAM_DQ[8] -set_location_assignment PIN_N2 -to DRAM_DQ[9] -set_location_assignment PIN_P1 -to DRAM_DQ[10] -set_location_assignment PIN_P2 -to DRAM_DQ[11] -set_location_assignment PIN_R1 -to DRAM_DQ[12] -set_location_assignment PIN_R2 -to DRAM_DQ[13] -set_location_assignment PIN_T1 -to DRAM_DQ[14] -set_location_assignment PIN_T2 -to DRAM_DQ[15] -set_location_assignment PIN_R7 -to DRAM_LDQM -set_location_assignment PIN_T5 -to DRAM_RAS_N -set_location_assignment PIN_M5 -to DRAM_UDQM -set_location_assignment PIN_R8 -to DRAM_WE_N -set_location_assignment PIN_AB20 -to FL_ADDR[0] -set_location_assignment PIN_AA14 -to FL_ADDR[1] -set_location_assignment PIN_Y16 -to FL_ADDR[2] -set_location_assignment PIN_R15 -to FL_ADDR[3] -set_location_assignment PIN_T15 -to FL_ADDR[4] -set_location_assignment PIN_U15 -to FL_ADDR[5] -set_location_assignment PIN_V15 -to FL_ADDR[6] -set_location_assignment PIN_W15 -to FL_ADDR[7] -set_location_assignment PIN_R14 -to FL_ADDR[8] -set_location_assignment PIN_Y13 -to FL_ADDR[9] -set_location_assignment PIN_R12 -to FL_ADDR[10] -set_location_assignment PIN_T12 -to FL_ADDR[11] -set_location_assignment PIN_AB14 -to FL_ADDR[12] -set_location_assignment PIN_AA13 -to FL_ADDR[13] -set_location_assignment PIN_AB13 -to FL_ADDR[14] -set_location_assignment PIN_AA12 -to FL_ADDR[15] -set_location_assignment PIN_AB12 -to FL_ADDR[16] -set_location_assignment PIN_AA20 -to FL_ADDR[17] -set_location_assignment PIN_U14 -to FL_ADDR[18] -set_location_assignment PIN_V14 -to FL_ADDR[19] -set_location_assignment PIN_U13 -to FL_ADDR[20] -set_location_assignment PIN_R13 -to FL_ADDR[21] -set_location_assignment PIN_AB16 -to FL_DQ[0] -set_location_assignment PIN_AA16 -to FL_DQ[1] -set_location_assignment PIN_AB17 -to FL_DQ[2] -set_location_assignment PIN_AA17 -to FL_DQ[3] -set_location_assignment PIN_AB18 -to FL_DQ[4] -set_location_assignment PIN_AA18 -to FL_DQ[5] -set_location_assignment PIN_AB19 -to FL_DQ[6] -set_location_assignment PIN_AA19 -to FL_DQ[7] -set_location_assignment PIN_AA15 -to FL_OE_N -set_location_assignment PIN_W14 -to FL_RST_N -set_location_assignment PIN_Y14 -to FL_WE_N -set_location_assignment PIN_AA3 -to SRAM_ADDR[0] -set_location_assignment PIN_AB3 -to SRAM_ADDR[1] -set_location_assignment PIN_AA4 -to SRAM_ADDR[2] -set_location_assignment PIN_AB4 -to SRAM_ADDR[3] -set_location_assignment PIN_AA5 -to SRAM_ADDR[4] -set_location_assignment PIN_AB10 -to SRAM_ADDR[5] -set_location_assignment PIN_AA11 -to SRAM_ADDR[6] -set_location_assignment PIN_AB11 -to SRAM_ADDR[7] -set_location_assignment PIN_V11 -to SRAM_ADDR[8] -set_location_assignment PIN_W11 -to SRAM_ADDR[9] -set_location_assignment PIN_R11 -to SRAM_ADDR[10] -set_location_assignment PIN_T11 -to SRAM_ADDR[11] -set_location_assignment PIN_Y10 -to SRAM_ADDR[12] -set_location_assignment PIN_U10 -to SRAM_ADDR[13] -set_location_assignment PIN_R10 -to SRAM_ADDR[14] -set_location_assignment PIN_T7 -to SRAM_ADDR[15] -set_location_assignment PIN_Y6 -to SRAM_ADDR[16] -set_location_assignment PIN_Y5 -to SRAM_ADDR[17] -set_location_assignment PIN_AB5 -to SRAM_CE_N -set_location_assignment PIN_AA6 -to SRAM_DQ[0] -set_location_assignment PIN_AB6 -to SRAM_DQ[1] -set_location_assignment PIN_AA7 -to SRAM_DQ[2] -set_location_assignment PIN_AB7 -to SRAM_DQ[3] -set_location_assignment PIN_AA8 -to SRAM_DQ[4] -set_location_assignment PIN_AB8 -to SRAM_DQ[5] -set_location_assignment PIN_AA9 -to SRAM_DQ[6] -set_location_assignment PIN_AB9 -to SRAM_DQ[7] -set_location_assignment PIN_Y9 -to SRAM_DQ[8] -set_location_assignment PIN_W9 -to SRAM_DQ[9] -set_location_assignment PIN_V9 -to SRAM_DQ[10] -set_location_assignment PIN_U9 -to SRAM_DQ[11] -set_location_assignment PIN_R9 -to SRAM_DQ[12] -set_location_assignment PIN_W8 -to SRAM_DQ[13] -set_location_assignment PIN_V8 -to SRAM_DQ[14] -set_location_assignment PIN_U8 -to SRAM_DQ[15] -set_location_assignment PIN_Y7 -to SRAM_LB_N -set_location_assignment PIN_T8 -to SRAM_OE_N -set_location_assignment PIN_W7 -to SRAM_UB_N -set_location_assignment PIN_AA10 -to SRAM_WE_N -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_134 -to VGA_R[1] +set_location_assignment PIN_133 -to VGA_R[2] +set_location_assignment PIN_132 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_G[0] +set_location_assignment PIN_142 -to VGA_G[1] +set_location_assignment PIN_143 -to VGA_G[2] +set_location_assignment PIN_144 -to VGA_G[3] +set_location_assignment PIN_4 -to VGA_B[0] +set_location_assignment PIN_7 -to VGA_B[1] +set_location_assignment PIN_10 -to VGA_B[2] +set_location_assignment PIN_11 -to VGA_B[3] +set_location_assignment PIN_136 -to VGA_HS +set_location_assignment PIN_137 -to VGA_VS set_global_assignment -name ENABLE_SIGNALTAP ON -set_location_assignment PIN_V20 -to SD_CLK -set_location_assignment PIN_Y20 -to SD_CMD -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_location_assignment PIN_44 -to SD_CLK +set_location_assignment PIN_46 -to SD_CMD set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF set_global_assignment -name BLOCK_DESIGN_NAMING AUTO set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_location_assignment PIN_W20 -to SD_DATA -set_location_assignment PIN_U20 -to SD_THREE set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED @@ -516,6 +87,104 @@ set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" + +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp +set_location_assignment PIN_28 -to AUDIO_L +set_location_assignment PIN_30 -to AUDIO_R +set_location_assignment PIN_53 -to CPU_RESET_n +set_location_assignment PIN_55 -to FPGA_CLK +set_location_assignment PIN_127 -to JOY1_n[0] +set_location_assignment PIN_91 -to JOY1_n[1] +set_location_assignment PIN_90 -to JOY1_n[2] +set_location_assignment PIN_88 -to JOY1_n[3] +set_location_assignment PIN_89 -to JOY1_n[4] +set_location_assignment PIN_126 -to JOY1_n[5] +set_location_assignment PIN_128 -to JOY2_n[0] +set_location_assignment PIN_25 -to JOY2_n[1] +set_location_assignment PIN_24 -to JOY2_n[2] +set_location_assignment PIN_22 -to JOY2_n[3] +set_location_assignment PIN_23 -to JOY2_n[4] +set_location_assignment PIN_129 -to JOY2_n[5] +set_location_assignment PIN_33 -to PS2K_DAT +set_location_assignment PIN_39 -to PS2K_CLK +set_location_assignment PIN_32 -to PS2M_DAT +set_location_assignment PIN_31 -to PS2M_CLK +set_location_assignment PIN_52 -to SD_DAT0 +set_location_assignment PIN_49 -to SD_DAT3 +set_location_assignment PIN_42 -to USB_P +set_location_assignment PIN_43 -to USB_N +set_location_assignment PIN_50 -to USB2_P +set_location_assignment PIN_51 -to USB2_N +set_location_assignment PIN_112 -to SDRAM_CLK +set_location_assignment PIN_61 -to SDRAM_A[0] +set_location_assignment PIN_60 -to SDRAM_A[1] +set_location_assignment PIN_59 -to SDRAM_A[2] +set_location_assignment PIN_58 -to SDRAM_A[3] +set_location_assignment PIN_125 -to SDRAM_A[4] +set_location_assignment PIN_121 -to SDRAM_A[5] +set_location_assignment PIN_120 -to SDRAM_A[6] +set_location_assignment PIN_119 -to SDRAM_A[7] +set_location_assignment PIN_115 -to SDRAM_A[8] +set_location_assignment PIN_114 -to SDRAM_A[9] +set_location_assignment PIN_64 -to SDRAM_A[10] +set_location_assignment PIN_113 -to SDRAM_A[11] +set_location_assignment PIN_111 -to SDRAM_A[12] +set_location_assignment PIN_66 -to SDRAM_BA[0] +set_location_assignment PIN_65 -to SDRAM_BA[1] +set_location_assignment PIN_87 -to SDRAM_DQ[0] +set_location_assignment PIN_86 -to SDRAM_DQ[1] +set_location_assignment PIN_85 -to SDRAM_DQ[2] +set_location_assignment PIN_83 -to SDRAM_DQ[3] +set_location_assignment PIN_80 -to SDRAM_DQ[4] +set_location_assignment PIN_79 -to SDRAM_DQ[5] +set_location_assignment PIN_77 -to SDRAM_DQ[6] +set_location_assignment PIN_76 -to SDRAM_DQ[7] +set_location_assignment PIN_106 -to SDRAM_DQ[8] +set_location_assignment PIN_105 -to SDRAM_DQ[9] +set_location_assignment PIN_104 -to SDRAM_DQ[10] +set_location_assignment PIN_103 -to SDRAM_DQ[11] +set_location_assignment PIN_101 -to SDRAM_DQ[12] +set_location_assignment PIN_100 -to SDRAM_DQ[13] +set_location_assignment PIN_99 -to SDRAM_DQ[14] +set_location_assignment PIN_98 -to SDRAM_DQ[15] +set_location_assignment PIN_67 -to SDRAM_CS_n +set_location_assignment PIN_68 -to SDRAM_RAS_n +set_location_assignment PIN_69 -to SDRAM_CAS_n +set_location_assignment PIN_71 -to SDRAM_WE_n +set_location_assignment PIN_6 -to CFG_DOUT +set_location_assignment PIN_8 -to CFG_CS_n +set_location_assignment PIN_12 -to CFG_CLK +set_location_assignment PIN_13 -to CFG_DIN +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_location_assignment PIN_72 -to SDRAM_DQM_n[0] +set_location_assignment PIN_110 -to SDRAM_DQM_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0] +set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 +set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v +set_global_assignment -name VHDL_FILE romlo.vhd +set_global_assignment -name VHDL_FILE romhi.vhd +set_global_assignment -name VHDL_FILE ramint.vhd set_global_assignment -name VHDL_FILE atari800core.vhd set_global_assignment -name VHDL_FILE spi_master.vhd set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl @@ -526,19 +195,12 @@ set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd -set_global_assignment -name VHDL_FILE i2s_intf.vhd -set_global_assignment -name VHDL_FILE i2c_loader.vhd set_global_assignment -name VHDL_FILE cpu.vhd -set_global_assignment -name VHDL_FILE ledsw.vhd -set_global_assignment -name VHDL_FILE hexdecoder.vhd set_global_assignment -name QIP_FILE pll.qip set_global_assignment -name SDC_FILE atari800core.sdc -set_global_assignment -name VHDL_FILE dumprom.vhdl set_global_assignment -name VHDL_FILE reg_file.vhdl set_global_assignment -name VHDL_FILE address_decoder.vhdl -set_global_assignment -name VHDL_FILE i2sslave.vhdl set_global_assignment -name VHDL_FILE pokey.vhdl -set_global_assignment -name VHDL_FILE nmigen.vhdl set_global_assignment -name VHDL_FILE enable_divider.vhdl set_global_assignment -name VHDL_FILE poly_17_9.vhdl set_global_assignment -name VHDL_FILE poly_5.vhdl @@ -548,11 +210,8 @@ set_global_assignment -name VHDL_FILE pokey_mixer.vhdl set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl -set_global_assignment -name VHDL_FILE tvsync.vhdl set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl -set_global_assignment -name VHDL_FILE flashrom.vhdl -set_global_assignment -name VHDL_FILE sram.vhdl set_global_assignment -name VHDL_FILE antic.vhdl set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl set_global_assignment -name VHDL_FILE antic_counter.vhdl @@ -569,18 +228,461 @@ set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd set_global_assignment -name VHDL_FILE wide_delay_line.vhdl set_global_assignment -name VHDL_FILE irq_glue.vhdl -set_global_assignment -name VHDL_FILE gpio.vhd set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl set_global_assignment -name VHDL_FILE zpu_glue.vhdl set_global_assignment -name QIP_FILE zpu_ram.qip set_global_assignment -name QIP_FILE zpu_rom.qip -set_location_assignment PIN_A13 -to GPIO_0[0] -set_location_assignment PIN_B13 -to GPIO_0[1] -set_location_assignment PIN_A14 -to GPIO_0[2] -set_location_assignment PIN_B14 -to GPIO_0[3] - -set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp +set_global_assignment -name VHDL_FILE internalromram.vhd +set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "sdram_statemachine_mcc:b2v_inst20|CLK_SDRAM" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "address_decoder:b2v_inst2|SDRAM_REQUEST" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "address_decoder:b2v_inst2|SDRAM_REQUEST_COMPLETE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "address_decoder:b2v_inst2|SDRAM_REQUEST" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "address_decoder:b2v_inst2|SDRAM_REQUEST_COMPLETE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "address_decoder:b2v_inst2|ZPU_ADDR[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "address_decoder:b2v_inst2|ZPU_ADDR[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "address_decoder:b2v_inst2|ZPU_ADDR[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "address_decoder:b2v_inst2|ZPU_ADDR[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "address_decoder:b2v_inst2|ZPU_ADDR[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "address_decoder:b2v_inst2|ZPU_ADDR[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "address_decoder:b2v_inst2|ZPU_ADDR[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "address_decoder:b2v_inst2|ZPU_ADDR[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "address_decoder:b2v_inst2|ZPU_ADDR[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "address_decoder:b2v_inst2|ZPU_ADDR[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "address_decoder:b2v_inst2|ZPU_ADDR[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "address_decoder:b2v_inst2|ZPU_ADDR[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "address_decoder:b2v_inst2|ZPU_ADDR[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "address_decoder:b2v_inst2|ZPU_ADDR[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "address_decoder:b2v_inst2|ZPU_ADDR[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "address_decoder:b2v_inst2|ZPU_ADDR[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "address_decoder:b2v_inst2|ZPU_ADDR[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "address_decoder:b2v_inst2|ZPU_ADDR[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "address_decoder:b2v_inst2|ZPU_ADDR[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "address_decoder:b2v_inst2|ZPU_ADDR[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "address_decoder:b2v_inst2|ZPU_ADDR[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "address_decoder:b2v_inst2|ZPU_ADDR[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "address_decoder:b2v_inst2|ZPU_ADDR[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "address_decoder:b2v_inst2|ZPU_ADDR[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "address_decoder:b2v_inst2|ZPU_FETCH" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "address_decoder:b2v_inst2|state_reg[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "address_decoder:b2v_inst2|state_reg[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sdram_statemachine_mcc:b2v_inst20|BYTE_ACCESS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "sdram_statemachine_mcc:b2v_inst20|LONGWORD_ACCESS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "sdram_statemachine_mcc:b2v_inst20|READ_EN" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "sdram_statemachine_mcc:b2v_inst20|REPLY" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "sdram_statemachine_mcc:b2v_inst20|REQUEST" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "address_decoder:b2v_inst2|ZPU_ADDR[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "address_decoder:b2v_inst2|ZPU_ADDR[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "address_decoder:b2v_inst2|ZPU_ADDR[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "address_decoder:b2v_inst2|ZPU_ADDR[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "address_decoder:b2v_inst2|ZPU_ADDR[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "address_decoder:b2v_inst2|ZPU_ADDR[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "address_decoder:b2v_inst2|ZPU_ADDR[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "address_decoder:b2v_inst2|ZPU_ADDR[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "address_decoder:b2v_inst2|ZPU_ADDR[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "address_decoder:b2v_inst2|ZPU_ADDR[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "address_decoder:b2v_inst2|ZPU_ADDR[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "address_decoder:b2v_inst2|ZPU_ADDR[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "address_decoder:b2v_inst2|ZPU_ADDR[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "address_decoder:b2v_inst2|ZPU_ADDR[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "address_decoder:b2v_inst2|ZPU_ADDR[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "address_decoder:b2v_inst2|ZPU_ADDR[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "address_decoder:b2v_inst2|ZPU_ADDR[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "address_decoder:b2v_inst2|ZPU_ADDR[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "address_decoder:b2v_inst2|ZPU_ADDR[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "address_decoder:b2v_inst2|ZPU_ADDR[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "address_decoder:b2v_inst2|ZPU_ADDR[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "address_decoder:b2v_inst2|ZPU_ADDR[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "address_decoder:b2v_inst2|ZPU_ADDR[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "address_decoder:b2v_inst2|ZPU_ADDR[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "address_decoder:b2v_inst2|ZPU_FETCH" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "address_decoder:b2v_inst2|state_reg[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "address_decoder:b2v_inst2|state_reg[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sdram_statemachine_mcc:b2v_inst20|BYTE_ACCESS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "sdram_statemachine_mcc:b2v_inst20|LONGWORD_ACCESS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "sdram_statemachine_mcc:b2v_inst20|READ_EN" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "sdram_statemachine_mcc:b2v_inst20|REPLY" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "sdram_statemachine_mcc:b2v_inst20|REQUEST" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA1" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CAS_N" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CS_N" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_RAS_N" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_WE_N" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ldqm" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_udqm" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "sdram_statemachine_mcc:b2v_inst20|WRITE_EN" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|fetch_b0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rden_b0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|valid_b0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wren_b0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA1" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CAS_N" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CS_N" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_RAS_N" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_WE_N" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ldqm" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_udqm" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "sdram_statemachine_mcc:b2v_inst20|WRITE_EN" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|fetch_b0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rden_b0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|valid_b0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wren_b0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[2]" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=221" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=221" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=686" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=45961" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=45082" -section_id auto_signaltap_0 - -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top Only in atari800core_v1_20140121_mcc216: atari800core.qsf.bak Binary files atari800core_20140301_de1/atari800core.qws and atari800core_v1_20140121_mcc216/atari800core.qws differ diff -ur atari800core_20140301_de1/atari800core.sdc atari800core_v1_20140121_mcc216/atari800core.sdc --- atari800core_20140301_de1/atari800core.sdc 2014-03-01 12:29:51.000000000 +0000 +++ atari800core_v1_20140121_mcc216/atari800core.sdc 2014-01-21 19:27:45.000000000 +0000 @@ -1,6 +1,3 @@ -create_clock -period 50MHz [get_ports CLOCK_50] -derive_pll_clocks - -set_input_delay -max -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*] -set_input_delay -min -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*] - +create_clock -period 5MHz [get_ports FPGA_CLK] +derive_pll_clocks +derive_clock_uncertainty \ No newline at end of file Only in atari800core_20140301_de1: atari800core.sdc~ Only in atari800core_v1_20140121_mcc216: atari800core.sdc.bak diff -ur atari800core_20140301_de1/atari800core.vhd atari800core_v1_20140121_mcc216/atari800core.vhd --- atari800core_20140301_de1/atari800core.vhd 2014-01-20 20:13:33.000000000 +0000 +++ atari800core_v1_20140121_mcc216/atari800core.vhd 2014-01-28 20:47:59.000000000 +0000 @@ -24,60 +24,39 @@ ENTITY atari800core IS PORT ( - CLOCK_50 : IN STD_LOGIC; - AUD_BCLK : IN STD_LOGIC; - AUD_DACLRCK : IN STD_LOGIC; - PS2_CLK : IN STD_LOGIC; - PS2_DAT : IN STD_LOGIC; - UART_RXD : IN STD_LOGIC; - SD_DATA : IN STD_LOGIC; - I2C_SCLK : INOUT STD_LOGIC; - I2C_SDAT : INOUT STD_LOGIC; - DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); - FL_DQ : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - GPIO_0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); - GPIO_1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); - KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); - SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); - AUD_XCK : OUT STD_LOGIC; - AUD_DACDAT : OUT STD_LOGIC; + FPGA_CLK : IN STD_LOGIC; + PS2K_CLK : IN STD_LOGIC; + PS2K_DAT : IN STD_LOGIC; + PS2M_CLK : IN STD_LOGIC; + PS2M_DAT : IN STD_LOGIC; + VGA_VS : OUT STD_LOGIC; VGA_HS : OUT STD_LOGIC; - FL_OE_N : OUT STD_LOGIC; - FL_WE_N : OUT STD_LOGIC; - FL_RST_N : OUT STD_LOGIC; - SRAM_CE_N : OUT STD_LOGIC; - SRAM_OE_N : OUT STD_LOGIC; - SRAM_WE_N : OUT STD_LOGIC; - SRAM_LB_N : OUT STD_LOGIC; - SRAM_UB_N : OUT STD_LOGIC; - UART_TXD : OUT STD_LOGIC; - DRAM_BA_0 : OUT STD_LOGIC; - DRAM_BA_1 : OUT STD_LOGIC; - DRAM_CS_N : OUT STD_LOGIC; - DRAM_RAS_N : OUT STD_LOGIC; - DRAM_CAS_N : OUT STD_LOGIC; - DRAM_WE_N : OUT STD_LOGIC; - DRAM_LDQM : OUT STD_LOGIC; - DRAM_UDQM : OUT STD_LOGIC; - DRAM_CLK : OUT STD_LOGIC; - DRAM_CKE : OUT STD_LOGIC; - SD_CLK : OUT STD_LOGIC; - SD_CMD : OUT STD_LOGIC; - SD_THREE : OUT STD_LOGIC; - DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - FL_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0); - HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); - HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); - HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); - HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); - LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); - SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + JOY1_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + JOY2_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + + AUDIO_L : OUT std_logic; + AUDIO_R : OUT std_logic; + + SDRAM_BA : OUT STD_LOGIC_VECTOR(1 downto 0); + SDRAM_CS_N : OUT STD_LOGIC; + SDRAM_RAS_N : OUT STD_LOGIC; + SDRAM_CAS_N : OUT STD_LOGIC; + SDRAM_WE_N : OUT STD_LOGIC; + SDRAM_DQM_n : OUT STD_LOGIC_vector(1 downto 0); + SDRAM_CLK : OUT STD_LOGIC; + --SDRAM_CKE : OUT STD_LOGIC; + SDRAM_A : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); + + SD_DAT0 : IN STD_LOGIC; + SD_CLK : OUT STD_LOGIC; + SD_CMD : OUT STD_LOGIC; + SD_DAT3 : OUT STD_LOGIC ); END atari800core; @@ -100,32 +79,35 @@ ); END COMPONENT; -COMPONENT hexdecoder - PORT(CLK : IN STD_LOGIC; - NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) - ); -END COMPONENT; +component hq_dac +port ( + reset :in std_logic; + clk :in std_logic; + clk_ena : in std_logic; + pcm_in : in std_logic_vector(19 downto 0); + dac_out : out std_logic +); +end component; -COMPONENT sram - PORT(WREN : IN STD_LOGIC; - clk : IN STD_LOGIC; - reset_n : IN STD_LOGIC; - request : IN STD_LOGIC; - width_16bit : IN STD_LOGIC; - ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0); - DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); - SRAM_CE_N : OUT STD_LOGIC; - SRAM_OE_N : OUT STD_LOGIC; - SRAM_WE_N : OUT STD_LOGIC; - SRAM_LB_N : OUT STD_LOGIC; - SRAM_UB_N : OUT STD_LOGIC; - complete : OUT STD_LOGIC; - DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0) +component internalromram IS + PORT( + clock : IN STD_LOGIC; --system clock + reset_n : IN STD_LOGIC; --asynchronous reset + + ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0); + ROM_REQUEST_COMPLETE : out STD_LOGIC; + ROM_REQUEST : in std_logic; + ROM_DATA : out std_logic_vector(7 downto 0); + + RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0); + RAM_WR_ENABLE : in std_logic; + RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0); + RAM_REQUEST_COMPLETE : out STD_LOGIC; + RAM_REQUEST : in std_logic; + RAM_DATA : out std_logic_vector(7 downto 0) ); -END COMPONENT; + +END component; COMPONENT antic PORT(CLK : IN STD_LOGIC; @@ -306,72 +288,11 @@ SYSTEM_RESET : OUT STD_LOGIC; KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + VIRTUAL_KEYS : out std_logic_vector(3 downto 0) ); END COMPONENT; -COMPONENT gpio - PORT( - clk : in std_logic; - - gpio_enable : in std_logic; - - -- pia - porta_in : out std_logic_vector(7 downto 0); - virtual_stick_in : in std_logic_vector(7 downto 0); - porta_out : in std_logic_vector(7 downto 0); - porta_output : in std_logic_vector(7 downto 0); - CA2_DIR_OUT : IN std_logic; - CA2_OUT : IN std_logic; - CA2_IN : OUT STD_LOGIC; - CB2_DIR_OUT : IN std_logic; - CB2_OUT : IN std_logic; - CB2_IN : OUT STD_LOGIC; - - -- gtia - virtual_trig_in : in std_logic_vector(3 downto 0); - trig_in : out std_logic_vector(3 downto 0); - - -- antic - lightpen : out std_logic; - - -- pokey - pot_reset : in std_logic; - pot_in : out std_logic_vector(7 downto 0); - keyboard_scan : in std_logic_vector(5 downto 0); - keyboard_response : out std_logic_vector(1 downto 0); - virtual_keycode : in std_logic_vector(5 downto 0); - virtual_keyheld : in std_logic; - virtual_shift_pressed : in std_logic; - virtual_control_pressed : in std_logic; - virtual_break_pressed : in std_logic; - SIO_IN : OUT STD_LOGIC; - SIO_OUT : IN STD_LOGIC; - - -- cartridge - pbi_addr_out : in std_logic_vector(15 downto 0); - pbi_write_enable : in std_logic; - cart_data_read : out std_logic_vector(7 downto 0); - cart_request : in std_logic; - cart_complete : out std_logic; - cart_data_write : in std_logic_vector(7 downto 0); - rd4 : out std_logic; - rd5 : out std_logic; - s4_n : in std_logic; - s5_n : in std_logic; - cctl_n : in std_logic; - - monitor : in std_logic; - - -- gpio connections - GPIO_0_IN : in std_logic_vector(35 downto 0); - GPIO_0_OUT : out std_logic_vector(35 downto 0); - GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0); - GPIO_1_IN : in std_logic_vector(35 downto 0); - GPIO_1_OUT : out std_logic_vector(35 downto 0); - GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0) - ); -END COMPONENT; COMPONENT address_decoder PORT(CLK : IN STD_LOGIC; @@ -391,7 +312,7 @@ CART_RD4 : IN STD_LOGIC; CART_RD5 : IN STD_LOGIC; use_sdram : IN STD_LOGIC; - SDRAM_REPLY : IN STD_LOGIC; + SDRAM_REQUEST_COMPLETE : IN STD_LOGIC; ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); @@ -480,6 +401,50 @@ ); END COMPONENT; +component sdram_statemachine_mcc IS +generic +( + ADDRESS_WIDTH : natural := 22; + ROW_WIDTH : natural := 12; + AP_BIT : natural := 10; + COLUMN_WIDTH : natural := 8 +); +PORT +( + CLK_SYSTEM : IN STD_LOGIC; + CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock + RESET_N : in STD_LOGIC; + + -- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here? + DATA_IN : in std_logic_vector(31 downto 0); + ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment + READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh + WRITE_EN : in std_logic; + REQUEST : in std_logic; -- Toggle this to issue a new request + BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0. + WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0. + LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000 + REFRESH : in std_logic; + + REPLY : out std_logic; -- This matches the request once complete + DATA_OUT : out std_logic_vector(31 downto 0); + + -- sdram itself + SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0); + SDRAM_DQ : inout std_logic_vector(15 downto 0); + SDRAM_BA0 : out std_logic; + SDRAM_BA1 : out std_logic; + + SDRAM_CS_N : out std_logic; + SDRAM_RAS_N : out std_logic; + SDRAM_CAS_N : out std_logic; + SDRAM_WE_N : out std_logic; + + SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads + SDRAM_udqm : out std_logic +); +END component; + COMPONENT zpu_rom PORT(clock : IN STD_LOGIC; address : IN STD_LOGIC_VECTOR(11 DOWNTO 0); @@ -551,36 +516,6 @@ ); END COMPONENT; -COMPONENT i2c_loader -GENERIC (device_address : INTEGER; - log2_divider : INTEGER; - num_retries : INTEGER - ); - PORT(CLK : IN STD_LOGIC; - nRESET : IN STD_LOGIC; - I2C_SCL : INOUT STD_LOGIC; - I2C_SDA : INOUT STD_LOGIC; - IS_DONE : OUT STD_LOGIC; - IS_ERROR : OUT STD_LOGIC - ); -END COMPONENT; - -COMPONENT flashrom - PORT(CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - REQUEST : IN STD_LOGIC; - ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0); - FLASH_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - FLASH_CE_N : OUT STD_LOGIC; - FLASH_OE_N : OUT STD_LOGIC; - FLASH_WE_N : OUT STD_LOGIC; - FLASH_RESET_N : OUT STD_LOGIC; - COMPLETE : OUT STD_LOGIC; - DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) - ); -END COMPONENT; - COMPONENT pll PORT(inclk0 : IN STD_LOGIC; c0 : OUT STD_LOGIC; @@ -590,17 +525,6 @@ ); END COMPONENT; -COMPONENT i2sslave - PORT(CLK : IN STD_LOGIC; - BCLK : IN STD_LOGIC; - DACLRC : IN STD_LOGIC; - LEFT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - RIGHT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - MCLK_2 : OUT STD_LOGIC; - DACDAT : OUT STD_LOGIC - ); -END COMPONENT; - COMPONENT gtia PORT(CLK : IN STD_LOGIC; WR_EN : IN STD_LOGIC; @@ -657,6 +581,7 @@ ); END component; + SIGNAL ANTIC_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL ANTIC_AN : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL ANTIC_COLOUR_CLOCK_OUT : STD_LOGIC; @@ -672,7 +597,7 @@ SIGNAL AUDIO_LEFT : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL AUDIO_RIGHT : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL BREAK_PRESSED : STD_LOGIC; -SIGNAL CART_CCTL_N : STD_LOGIC; + SIGNAL CART_RD4 : STD_LOGIC; SIGNAL CART_RD5 : STD_LOGIC; SIGNAL CART_REQUEST : STD_LOGIC; @@ -680,6 +605,7 @@ SIGNAL CART_ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CART_S4_n : STD_LOGIC; SIGNAL CART_S5_N : STD_LOGIC; +signal CART_CCTL_N : std_logic; SIGNAL CA2_OUT : STD_LOGIC; SIGNAL CA2_DIR_OUT: STD_LOGIC; SIGNAL CB2_OUT : STD_LOGIC; @@ -770,7 +696,8 @@ SIGNAL SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL SDRAM_READ_ENABLE : STD_LOGIC; SIGNAL SDRAM_REFRESH : STD_LOGIC; -SIGNAL SDRAM_REPLY : STD_LOGIC; +--SIGNAL SDRAM_REPLY : STD_LOGIC; +SIGNAL SDRAM_REQUEST_COMPLETE : STD_LOGIC; SIGNAL SDRAM_REQUEST : STD_LOGIC; SIGNAL SDRAM_WRITE_ENABLE : STD_LOGIC; SIGNAL SHIFT_PRESSED : STD_LOGIC; @@ -786,6 +713,7 @@ SIGNAL VGA : STD_LOGIC; SIGNAL VIRTUAL_STICKS : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL VIRTUAL_TRIGGERS : STD_LOGIC_VECTOR(3 DOWNTO 0); +SIGNAL VIRTUAL_KEYS : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL WIDTH_16BIT_ACCESS : STD_LOGIC; SIGNAL WIDTH_32BIT_ACCESS : STD_LOGIC; SIGNAL WIDTH_8BIT_ACCESS : STD_LOGIC; @@ -822,6 +750,9 @@ SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL LEDR_dummy : STD_LOGIC_VECTOR(9 DOWNTO 0); +SIGNAL LEDG_dummy : STD_LOGIC_VECTOR(7 DOWNTO 0); +signal UART_TXD_dummy : std_logic; BEGIN @@ -842,50 +773,7 @@ A => CPU_ADDR, DO => CPU_DO); - -b2v_hex0_inst : hexdecoder -PORT MAP(CLK => CLK, - NUMBER => ZPU_HEX(3 DOWNTO 0), - DIGIT => HEX0); - - -b2v_hex0_inst2 : hexdecoder -PORT MAP(CLK => CLK, - NUMBER => ZPU_HEX(7 DOWNTO 4), - DIGIT => HEX1); - - -b2v_hex0_inst3 : hexdecoder -PORT MAP(CLK => CLK, - NUMBER => ZPU_HEX(11 DOWNTO 8), - DIGIT => HEX2); - - -b2v_hex0_inst4 : hexdecoder -PORT MAP(CLK => CLK, - NUMBER => ZPU_HEX(15 DOWNTO 12), - DIGIT => HEX3); - - -b2v_inst : sram -PORT MAP(WREN => RAM_WRITE_ENABLE, - clk => CLK, - reset_n => RESET_N, - request => RAM_REQUEST, - width_16bit => WIDTH_16BIT_ACCESS, - ADDRESS => RAM_ADDR, - DIN => WRITE_DATA(15 DOWNTO 0), - SRAM_DQ => SRAM_DQ, - SRAM_CE_N => SRAM_CE_N, - SRAM_OE_N => SRAM_OE_N, - SRAM_WE_N => SRAM_WE_N, - SRAM_LB_N => SRAM_LB_N, - SRAM_UB_N => SRAM_UB_N, - complete => RAM_REQUEST_COMPLETE, - DOUT => RAM_DO, - SRAM_ADDR => SRAM_ADDR); - - +LIGHTPEN <= '1'; b2v_inst1 : antic PORT MAP(CLK => CLK, WR_EN => ANTIC_WRITE_ENABLE, @@ -909,15 +797,6 @@ DATA_OUT => ANTIC_DO, dma_address_out => ANTIC_ADDR); - -b2v_inst10 : ledsw -PORT MAP(CLK => CLK, - KEY => KEY, - SW => SW, - SYNC_KEYS => SYNC_KEYS, - SYNC_SWITCHES => SYNC_SWITCHES); - - b2v_inst11 : pokey_mixer PORT MAP(CLK => CLK, GTIA_SOUND => GTIA_SOUND, @@ -927,13 +806,33 @@ CHANNEL_3 => SYNTHESIZED_WIRE_3, CHANNEL_ENABLE => "1111", VOLUME_OUT => AUDIO_LEFT); + +dac_left : hq_dac +port map +( + reset => not(reset_n), + clk => clk, + clk_ena => '1', + pcm_in => audio_left&"0000", + dac_out => audio_l +); + +dac_right : hq_dac +port map +( + reset => not(reset_n), + clk => clk, + clk_ena => '1', + pcm_in => audio_right&"0000", + dac_out => audio_r +); b2v_inst12 : ps2_keyboard PORT MAP(CLK => CLK, RESET_N => RESET_N, - PS2_CLK => PS2_CLK, - PS2_DAT => PS2_DAT, + PS2_CLK => PS2K_CLK, + PS2_DAT => PS2K_DAT, KEY_EVENT => SYNTHESIZED_WIRE_8, KEY_EXTENDED => SYNTHESIZED_WIRE_9, KEY_UP => SYNTHESIZED_WIRE_10, @@ -1001,6 +900,9 @@ SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin -- TODO - sioto gpio! GPIO_PORTB_IN <= PORTB_OUT; +GPIO_CA2_IN <= CA2_OUT; +GPIO_CB2_IN <= CB2_OUT; +GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3)); b2v_inst16 : pia PORT MAP(CLK => CLK, @@ -1058,65 +960,14 @@ SYSTEM_RESET => SYSTEM_RESET_REQUEST, KBCODE => KBCODE, VIRTUAL_STICKS => VIRTUAL_STICKS, - VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS); - -gpio0_gen: - for I in 0 to 35 generate - gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z'; - end generate gpio0_gen; - -gpio1_gen: - for I in 0 to 35 generate - gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z'; - end generate gpio1_gen; - -b2v_inst19 : gpio -PORT MAP(clk => CLK, - gpio_enable => GPIO_ENABLE, - pot_reset => POT_RESET, - virtual_keyheld => KEY_HELD, - virtual_shift_pressed => SHIFT_PRESSED, - virtual_control_pressed => KBCODE(7), - virtual_break_pressed => BREAK_PRESSED, - pbi_write_enable => PBI_WRITE_ENABLE, - cart_request => CART_REQUEST, - s4_n => CART_S4_n, - s5_n => CART_S5_N, - cctl_n => CART_CCTL_N, - cart_data_write => WRITE_DATA(7 DOWNTO 0), - GPIO_0_IN => GPIO_0, - GPIO_0_OUT => GPIO_0_OUT, - GPIO_0_DIR_OUT => GPIO_0_DIR_OUT, - GPIO_1_IN => GPIO_1, - GPIO_1_OUT => GPIO_1_OUT, - GPIO_1_DIR_OUT => GPIO_1_DIR_OUT, - keyboard_scan => KEYBOARD_SCAN, - pbi_addr_out => PBI_ADDR, - porta_out => PORTA_OUT, - porta_output => PORTA_DIR_OUT, - virtual_keycode => KBCODE(5 DOWNTO 0), - virtual_stick_in => VIRTUAL_STICKS, - virtual_trig_in => VIRTUAL_TRIGGERS, - lightpen => LIGHTPEN, - cart_complete => CART_REQUEST_COMPLETE, - rd4 => CART_RD4, - rd5 => CART_RD5, - cart_data_read => CART_ROM_DO, - keyboard_response => KEYBOARD_RESPONSE, - porta_in => GPIO_PORTA_IN, - pot_in => POT_IN, - trig_in => TRIGGERS, - monitor => SIO_DATA_IN, -- i.e. zpu sio out - CA2_DIR_OUT => CA2_DIR_OUT, - CA2_OUT => CA2_OUT, - CA2_IN => GPIO_CA2_IN, - CB2_DIR_OUT => CB2_DIR_OUT, - CB2_OUT => CB2_OUT, - CB2_IN => GPIO_CB2_IN, - SIO_IN => GPIO_SIO_IN, - SIO_OUT => GPIO_SIO_OUT - ); + VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS, + VIRTUAL_KEYS => VIRTUAL_KEYS); +-- no cart! +CART_RD4 <= '0'; +CART_RD5 <= '0'; +CART_REQUEST_COMPLETE <= '0'; +CART_ROM_DO <= (others=>'0'); b2v_inst2 : address_decoder PORT MAP(CLK => CLK, @@ -1136,7 +987,7 @@ CART_RD4 => CART_RD4, CART_RD5 => CART_RD5, use_sdram => USE_SDRAM, - SDRAM_REPLY => SDRAM_REPLY, + SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE, ANTIC_ADDR => ANTIC_ADDR, ANTIC_DATA => ANTIC_DO, CACHE_ANTIC_DATA => CACHE_ANTIC_DO, @@ -1189,40 +1040,6 @@ SDRAM_ADDR => SDRAM_ADDR, WRITE_DATA => WRITE_DATA); - -b2v_inst20 : sdram_statemachine -GENERIC MAP(ADDRESS_WIDTH => 22, - AP_BIT => 10, - COLUMN_WIDTH => 8, - ROW_WIDTH => 12 - ) -PORT MAP(CLK_SYSTEM => CLK, - CLK_SDRAM => CLK_SDRAM, - RESET_N => RESET_N, - READ_EN => SDRAM_READ_ENABLE, - WRITE_EN => SDRAM_WRITE_ENABLE, - REQUEST => SDRAM_REQUEST, - BYTE_ACCESS => WIDTH_8BIT_ACCESS, - WORD_ACCESS => WIDTH_16BIT_ACCESS, - LONGWORD_ACCESS => WIDTH_32BIT_ACCESS, - REFRESH => SDRAM_REFRESH, - ADDRESS_IN => SDRAM_ADDR, - DATA_IN => WRITE_DATA, - SDRAM_DQ => DRAM_DQ, - REPLY => SDRAM_REPLY, - SDRAM_BA0 => DRAM_BA_0, - SDRAM_BA1 => DRAM_BA_1, - SDRAM_CKE => DRAM_CKE, - SDRAM_CS_N => DRAM_CS_N, - SDRAM_RAS_N => DRAM_RAS_N, - SDRAM_CAS_N => DRAM_CAS_N, - SDRAM_WE_N => DRAM_WE_N, - SDRAM_ldqm => DRAM_LDQM, - SDRAM_udqm => DRAM_UDQM, - DATA_OUT => SDRAM_DO, - SDRAM_ADDR => DRAM_ADDR); - - b2v_inst21 : zpu_rom PORT MAP(clock => CLK, address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2), @@ -1253,23 +1070,24 @@ data => ZPU_DO(23 DOWNTO 16), q => ZPU_RAM_DATA(23 DOWNTO 16)); - +SYNC_KEYS <= (others=> '0'); +SYNC_SWITCHES <= (others=> '1'); b2v_inst24 : zpu_config_regs PORT MAP(CLK => CLK, ENABLE_179 => POKEY_ENABLE_179, WR_EN => ZPU_CONFIG_WRITE_ENABLE, - SDCARD_DAT => SD_DATA, + SDCARD_DAT => SD_DAT0, SIO_COMMAND_OUT => SIO_COMMAND_OUT, SIO_DATA_OUT => SIO_DATA_OUT, PLL_LOCKED => PLL_LOCKED, REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST, ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2), CPU_DATA_IN => ZPU_DO, - KEY => SYNC_KEYS, + KEY => VIRTUAL_KEYS, --SYNC_KEYS, SWITCH => SYNC_SWITCHES, SDCARD_CLK => SD_CLK, SDCARD_CMD => SD_CMD, - SDCARD_DAT3 => SD_THREE, + SDCARD_DAT3 => SD_DAT3, SIO_DATA_IN => SIO_DATA_IN, PAUSE_ZPU => ZPU_PAUSE, PAL => PAL, @@ -1282,8 +1100,8 @@ RESET_N => RESET_N, PAUSE_6502 => PAUSE_6502, DATA_OUT => ZPU_CONFIG_DO, - LEDG => LEDG, - LEDR => LEDR, + LEDG => LEDG_dummy, + LEDR => LEDR_dummy, RAM_SELECT => RAM_SELECT, ROM_SELECT => ROM_SELECT, THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502, @@ -1314,64 +1132,28 @@ q => ZPU_RAM_DATA(15 DOWNTO 8)); -b2v_inst3 : i2c_loader -GENERIC MAP(device_address => 26, - log2_divider => 6, - num_retries => 0 - ) -PORT MAP(CLK => CLK, - nRESET => RESET_N, - I2C_SCL => I2C_SCLK, - I2C_SDA => I2C_SDAT); - - -b2v_inst4 : flashrom -PORT MAP(CLK => CLK, - RESET_N => RESET_N, - REQUEST => ROM_REQUEST, - ADDRESS => ROM_ADDR, - FLASH_D => FL_DQ, - FLASH_OE_N => FL_OE_N, - FLASH_WE_N => FL_WE_N, - FLASH_RESET_N => FL_RST_N, - COMPLETE => ROM_REQUEST_COMPLETE, - DOUT => ROM_DO, - FLASH_ADDRESS => FL_ADDR); - - b2v_inst5 : pll -PORT MAP(inclk0 => CLOCK_50, +PORT MAP(inclk0 => FPGA_CLK, c0 => CLK_SDRAM, c1 => CLK, - c2 => DRAM_CLK, + c2 => SDRAM_CLK, locked => PLL_LOCKED); - -b2v_inst6 : i2sslave -PORT MAP(CLK => CLK, - BCLK => AUD_BCLK, - DACLRC => AUD_DACLRCK, - LEFT_IN => AUDIO_LEFT, - RIGHT_IN => AUDIO_RIGHT, - MCLK_2 => AUD_XCK, - DACDAT => AUD_DACDAT); - - b2v_inst7 : pokey PORT MAP(CLK => CLK, CPU_MEMORY_READY => MEMORY_READY_CPU, ANTIC_MEMORY_READY => MEMORY_READY_ANTIC, WR_EN => POKEY_WRITE_ENABLE, RESET_N => RESET_N, - SIO_IN1 => UART_RXD, - SIO_IN2 => GPIO_SIO_IN, + SIO_IN1 => '1', + SIO_IN2 => '1', SIO_IN3 => SIO_DATA_IN, ADDR => PBI_ADDR(3 DOWNTO 0), DATA_IN => WRITE_DATA(7 DOWNTO 0), keyboard_response => KEYBOARD_RESPONSE, POT_IN => POT_IN, IRQ_N_OUT => POKEY_IRQ, - SIO_OUT1 => UART_TXD, + SIO_OUT1 => UART_TXD_dummy, SIO_OUT2 => GPIO_SIO_OUT, SIO_OUT3 => SIO_DATA_OUT, POT_RESET => POT_RESET, @@ -1382,6 +1164,27 @@ DATA_OUT => POKEY_DO, keyboard_scan => KEYBOARD_SCAN); + process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed) + begin + keyboard_response <= (others=>'1'); + + if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then + keyboard_response(0) <= '0'; + end if; + + if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then + keyboard_response(1) <= '0'; + end if; + + if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then + keyboard_response(1) <= '0'; + end if; + + if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then + keyboard_response(1) <= '0'; + end if; + end process; + b2v_inst8 : gtia PORT MAP(CLK => CLK, WR_EN => GTIA_WRITE_ENABLE, @@ -1397,10 +1200,12 @@ CONSOL_START => CONSOL_START, CONSOL_SELECT => CONSOL_SELECT, CONSOL_OPTION => CONSOL_OPTION, - TRIG0 => TRIGGERS(0), - TRIG1 => TRIGGERS(1), - TRIG2 => TRIGGERS(2), - TRIG3 => TRIGGERS(3), + TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too + TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4), + --TRIG0 => VIRTUAL_TRIGGERS(0), + --TRIG1 => VIRTUAL_TRIGGERS(1), + TRIG2 => VIRTUAL_TRIGGERS(2), + TRIG3 => VIRTUAL_TRIGGERS(3), ADDR => PBI_ADDR(4 DOWNTO 0), AN => ANTIC_AN, CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0), @@ -1458,4 +1263,87 @@ DATA_OUT => CACHE_ANTIC_DO ); +irr : internalromram + PORT map( + clock => clk, + reset_n => reset_n, + + ROM_ADDR =>rom_addr, + ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE, + ROM_REQUEST => rom_REQUEST, + ROM_DATA => rom_DO, + + RAM_ADDR => ram_addr, + RAM_WR_ENABLE => ram_WRITE_ENABLE, + RAM_DATA_IN => wriTE_DATA(7 downto 0), + RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE, + RAM_REQUEST => ram_REQUEST, + RAM_DATA => ram_do(7 downto 0) + ); + +--b2v_inst20 : sdram_statemachine +--GENERIC MAP(ADDRESS_WIDTH => 22, +-- AP_BIT => 10, +-- COLUMN_WIDTH => 8, +-- ROW_WIDTH => 12 +-- ) +--PORT MAP(CLK_SYSTEM => CLK, +-- CLK_SDRAM => CLK_SDRAM, +-- RESET_N => RESET_N, +-- READ_EN => SDRAM_READ_ENABLE, +-- WRITE_EN => SDRAM_WRITE_ENABLE, +-- REQUEST => SDRAM_REQUEST, +-- BYTE_ACCESS => WIDTH_8BIT_ACCESS, +-- WORD_ACCESS => WIDTH_16BIT_ACCESS, +-- LONGWORD_ACCESS => WIDTH_32BIT_ACCESS, +-- REFRESH => SDRAM_REFRESH, +-- ADDRESS_IN => SDRAM_ADDR, +-- DATA_IN => WRITE_DATA, +-- SDRAM_DQ => SDRAM_DQ, +-- REPLY => SDRAM_REPLY, +-- SDRAM_BA0 => SDRAM_BA(0), +-- SDRAM_BA1 => SDRAM_BA(1), +-- SDRAM_CKE => SDRAM_A(12), +-- SDRAM_CS_N => SDRAM_CS_N, +-- SDRAM_RAS_N => SDRAM_RAS_N, +-- SDRAM_CAS_N => SDRAM_CAS_N, +-- SDRAM_WE_N => SDRAM_WE_N, +-- SDRAM_ldqm => SDRAM_DQM_n(0), +-- SDRAM_udqm => SDRAM_DQM_n(1), +-- DATA_OUT => SDRAM_DO, +-- SDRAM_ADDR => SDRAM_A(11 downto 0)); + +b2v_inst20 : sdram_statemachine_mcc +GENERIC MAP(ADDRESS_WIDTH => 22, + AP_BIT => 10, + COLUMN_WIDTH => 8, + ROW_WIDTH => 12 + ) +PORT MAP(CLK_SYSTEM => CLK, + CLK_SDRAM => CLK_SDRAM, + RESET_N => RESET_N, + READ_EN => SDRAM_READ_ENABLE, + WRITE_EN => SDRAM_WRITE_ENABLE, + REQUEST => SDRAM_REQUEST, + BYTE_ACCESS => WIDTH_8BIT_ACCESS, + WORD_ACCESS => WIDTH_16BIT_ACCESS, + LONGWORD_ACCESS => WIDTH_32BIT_ACCESS, + REFRESH => SDRAM_REFRESH, + ADDRESS_IN => SDRAM_ADDR, + DATA_IN => WRITE_DATA, + SDRAM_DQ => SDRAM_DQ, + REPLY => SDRAM_REQUEST_COMPLETE, + SDRAM_BA0 => SDRAM_BA(0), + SDRAM_BA1 => SDRAM_BA(1), + --SDRAM_CKE => SDRAM_A(12), -- TODO? + SDRAM_CS_N => SDRAM_CS_N, + SDRAM_RAS_N => SDRAM_RAS_N, + SDRAM_CAS_N => SDRAM_CAS_N, + SDRAM_WE_N => SDRAM_WE_N, + SDRAM_ldqm => SDRAM_DQM_n(0), + SDRAM_udqm => SDRAM_DQM_n(1), + DATA_OUT => SDRAM_DO, + SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO? + + END bdf_type; \ No newline at end of file Only in atari800core_v1_20140121_mcc216: hq_dac.v Only in atari800core_v1_20140121_mcc216: internalromram.vhd Only in atari800core_v1_20140121_mcc216: internalromram.vhd.bak Only in atari800core_v1_20140121_mcc216: pll.bsf diff -ur atari800core_20140301_de1/pll.cmp atari800core_v1_20140121_mcc216/pll.cmp --- atari800core_20140301_de1/pll.cmp 2014-01-17 20:20:16.000000000 +0000 +++ atari800core_v1_20140121_mcc216/pll.cmp 2014-01-26 09:19:13.000000000 +0000 @@ -1,25 +1,25 @@ ---Copyright (C) 1991-2012 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component pll - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2012 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component pll + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; Only in atari800core_v1_20140121_mcc216: PLLJ_PLLSPE_INFO.txt diff -ur atari800core_20140301_de1/pll.ppf atari800core_v1_20140121_mcc216/pll.ppf --- atari800core_20140301_de1/pll.ppf 2014-01-17 20:20:16.000000000 +0000 +++ atari800core_v1_20140121_mcc216/pll.ppf 2014-01-26 09:19:13.000000000 +0000 @@ -1,12 +1,12 @@ - - - - - - - - - - - - + + + + + + + + + + + + diff -ur atari800core_20140301_de1/pll.qip atari800core_v1_20140121_mcc216/pll.qip --- atari800core_20140301_de1/pll.qip 2014-01-17 20:20:16.000000000 +0000 +++ atari800core_v1_20140121_mcc216/pll.qip 2014-01-26 09:19:14.000000000 +0000 @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "12.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "12.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff -ur atari800core_20140301_de1/pll.vhd atari800core_v1_20140121_mcc216/pll.vhd --- atari800core_20140301_de1/pll.vhd 2014-01-17 20:20:16.000000000 +0000 +++ atari800core_v1_20140121_mcc216/pll.vhd 2014-01-26 09:19:13.000000000 +0000 @@ -1,427 +1,424 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2012 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - compensate_clock : STRING; - gate_lock_counter : NATURAL; - gate_lock_signal : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - invalid_lock_multiplier : NATURAL; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - valid_lock_multiplier : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - locked <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - clk0_divide_by => 10, - clk0_duty_cycle => 50, - clk0_multiply_by => 23, - clk0_phase_shift => "0", - clk1_divide_by => 20, - clk1_duty_cycle => 50, - clk1_multiply_by => 23, - clk1_phase_shift => "0", - clk2_divide_by => 10, - clk2_duty_cycle => 50, - clk2_multiply_by => 23, - clk2_phase_shift => "-1280", - compensate_clock => "CLK0", - gate_lock_counter => 1048575, - gate_lock_signal => "YES", - inclk0_input_frequency => 20000, - intended_device_family => "Cyclone II", - invalid_lock_multiplier => 5, - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - valid_lock_multiplier => 1 - ) - PORT MAP ( - inclk => sub_wire6, - clk => sub_wire0, - locked => sub_wire2 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "115.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "115.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "23" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "23" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "23" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575" --- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" --- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" --- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2012 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 2, + clk0_duty_cycle => 50, + clk0_multiply_by => 23, + clk0_phase_shift => "0", + clk1_divide_by => 2, + clk1_duty_cycle => 50, + clk1_multiply_by => 23, + clk1_phase_shift => "0", + clk2_divide_by => 2, + clk2_duty_cycle => 50, + clk2_multiply_by => 23, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 200000, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "20" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.500000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON Only in atari800core_v1_20140121_mcc216: pll.vhd.bak diff -ur atari800core_20140301_de1/pokey_ps2_decoder.vhdl atari800core_v1_20140121_mcc216/pokey_ps2_decoder.vhdl --- atari800core_20140301_de1/pokey_ps2_decoder.vhdl 2014-01-17 20:20:16.000000000 +0000 +++ atari800core_v1_20140121_mcc216/pokey_ps2_decoder.vhdl 2014-01-26 19:29:53.000000000 +0000 @@ -37,7 +37,9 @@ VIRTUAL_STICKS : out std_logic_vector(7 downto 0); VIRTUAL_TRIGGER : out std_logic_vector(3 downto 0); - SYSTEM_RESET : out std_logic + SYSTEM_RESET : out std_logic; + + VIRTUAL_KEYS : out std_logic_vector(3 downto 0) ); END pokey_ps2_decoder; @@ -84,6 +86,9 @@ signal system_reset_next : std_logic; signal system_reset_reg : std_logic; + + signal virtual_keys_next : std_logic_vector(3 downto 0); + signal virtual_keys_reg : std_logic_vector(3 downto 0); signal no_kbcode_update : std_logic; BEGIN @@ -116,6 +121,8 @@ virtual_stick_pressed_reg <= '0'; system_reset_reg <= '0'; + + virtual_keys_reg <= (others=>'0'); elsif (clk'event and clk='1') then left_shift_pressed_reg <= left_shift_pressed_next; right_shift_pressed_reg <= right_shift_pressed_next; @@ -142,11 +149,12 @@ virtual_stick_pressed_reg <= virtual_stick_pressed_next; system_reset_reg <= system_reset_next; + virtual_keys_reg <= virtual_keys_next; end if; end process; -- update key pressed - process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg) + process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg, virtual_keys_reg) begin left_shift_pressed_next <= left_shift_pressed_reg; right_shift_pressed_next <= right_shift_pressed_reg; @@ -170,6 +178,7 @@ virtual_stick_pressed_next <= virtual_stick_pressed_reg; system_reset_next <= system_reset_reg; + virtual_keys_next <= virtual_keys_reg; key_held_next <= key_held_reg; @@ -377,7 +386,31 @@ no_kbcode_update <= '1'; virtual_stick_pressed_next <= not(key_UP); interrupt_next <= '0'; - key_held_next <= '0'; + key_held_next <= '0'; + + when '0'&X"0a" => -- f8 => system reset + no_kbcode_update <= '1'; + virtual_keys_next(0) <= not(key_UP); + interrupt_next <= '0'; + key_held_next <= '0'; + + when '0'&X"01" => -- f9 => system reset + no_kbcode_update <= '1'; + virtual_keys_next(1) <= not(key_UP); + interrupt_next <= '0'; + key_held_next <= '0'; + + when '0'&X"09" => -- f10 => system reset + no_kbcode_update <= '1'; + virtual_keys_next(2) <= not(key_UP); + interrupt_next <= '0'; + key_held_next <= '0'; + + when '0'&X"78" => -- f11 => system reset + no_kbcode_update <= '1'; + virtual_keys_next(3) <= not(key_UP); + interrupt_next <= '0'; + key_held_next <= '0'; when '0'&X"07" => -- f12 => system reset no_kbcode_update <= '1'; @@ -430,5 +463,6 @@ VIRTUAL_TRIGGER <= "00"¬(virtual_stick_pressed_reg)¬(virtual_stick_pressed_reg); system_reset <= system_reset_reg; + virtual_keys <= virtual_keys_reg; END vhdl; \ No newline at end of file Only in atari800core_v1_20140121_mcc216: pokey_ps2_decoder.vhdl.bak Only in atari800core_v1_20140121_mcc216: ramint.bsf Only in atari800core_v1_20140121_mcc216: ramint.cmp Only in atari800core_v1_20140121_mcc216: ramint.qip Only in atari800core_v1_20140121_mcc216: ramint.vhd Only in atari800core_v1_20140121_mcc216: romhi.bsf Only in atari800core_v1_20140121_mcc216: romhi.cmp Only in atari800core_v1_20140121_mcc216: romhi.qip Only in atari800core_v1_20140121_mcc216: romhi.vhd Only in atari800core_v1_20140121_mcc216: romlo.bsf Only in atari800core_v1_20140121_mcc216: romlo.cmp Only in atari800core_v1_20140121_mcc216: romlo.qip Only in atari800core_v1_20140121_mcc216: romlo.vhd Only in atari800core_v1_20140121_mcc216: sdram_ctrl_4_ports.v Only in atari800core_v1_20140121_mcc216: sdram_ctrl_4_ports.v.bak Only in atari800core_v1_20140121_mcc216: sdram_statemachine_mcc.vhdl Only in atari800core_v1_20140121_mcc216: sdram_statemachine_mcc.vhdl.bak diff -ur atari800core_20140301_de1/sdram_statemachine.vhdl atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl --- atari800core_20140301_de1/sdram_statemachine.vhdl 2014-01-17 20:20:16.000000000 +0000 +++ atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl 2014-01-22 21:37:54.000000000 +0000 @@ -204,8 +204,8 @@ ras_n_reg <= '0'; cas_n_reg <= '0'; we_n_reg <= '0'; - ldqm_reg <= '1'; - udqm_reg <= '1'; + ldqm_reg <= '0'; + udqm_reg <= '0'; cke_reg <= '0'; --bank_row_reg <= (others=>(others=>'0')); Only in atari800core_v1_20140121_mcc216: sdram_statemachine.vhdl.bak diff -ur atari800core_20140301_de1/zpu/HelloTinyROM_ROM.mif atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif --- atari800core_20140301_de1/zpu/HelloTinyROM_ROM.mif 2014-01-20 21:22:00.000000000 +0000 +++ atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif 2014-01-31 21:09:40.000000000 +0000 @@ -170,7 +170,7 @@ 009f : 00000000; 00a0 : 71fc0608; 00a1 : 0b0b80f5; -00a2 : 98738306; +00a2 : d0738306; 00a3 : 10100508; 00a4 : 060b0b0b; 00a5 : 88a20400; @@ -216,8 +216,8 @@ 00cd : 00000000; 00ce : 00000000; 00cf : 00000000; -00d0 : 810b80fa; -00d1 : ec0c5104; +00d0 : 810b80fb; +00d1 : ac0c5104; 00d2 : 00000000; 00d3 : 00000000; 00d4 : 00000000; @@ -290,7 +290,7 @@ 0117 : 83e08408; 0118 : 83e08808; 0119 : 757580ef; -011a : c72d5050; +011a : fe2d5050; 011b : 83e08008; 011c : 5683e088; 011d : 0c83e084; @@ -299,7 +299,7 @@ 0120 : e0800883; 0121 : e0840883; 0122 : e0880875; -0123 : 7580eddb; +0123 : 7580ee92; 0124 : 2d505083; 0125 : e0800856; 0126 : 83e0880c; @@ -308,11 +308,11 @@ 0129 : 51040000; 012a : 800489aa; 012b : 0489aa0b; -012c : 80c0b404; +012c : 80c1a404; 012d : fd3d0d75; 012e : b9297681; 012f : 2a0580fd; -0130 : bc085473; +0130 : fc085473; 0131 : 0c853d0d; 0132 : 04803d0d; 0133 : 81ff5180; @@ -321,10 +321,10 @@ 0136 : 5170f438; 0137 : 823d0d04; 0138 : fa3d0d78; -0139 : 0b0b80f5; -013a : f05383e2; +0139 : 0b0b80f6; +013a : a85383e2; 013b : f4525680; -013c : cd9a3f80; +013c : cdd13f80; 013d : 5383e080; 013e : 08732e8a; 013f : 387283e0; @@ -332,7 +332,7 @@ 0141 : 0d0483e0; 0142 : 945283e2; 0143 : f45180ce; -0144 : 8e3f83e0; +0144 : c53f83e0; 0145 : 800880d5; 0146 : 3883e09d; 0147 : 33537280; @@ -362,9 +362,9 @@ 015f : e0800c88; 0160 : 3d0d04fd; 0161 : 3d0d800b; -0162 : 80fdac08; +0162 : 80fdec08; 0163 : 5353ff72; -0164 : 0c80fdb0; +0164 : 0c80fdf0; 0165 : 0873710c; 0166 : 5284d851; 0167 : fe963f88; @@ -373,10 +373,10 @@ 016a : 553472a8; 016b : 800a2e09; 016c : 8106f038; -016d : 80fdac08; +016d : 80fdec08; 016e : 5485aad5; 016f : aad5740c; -0170 : 80fdb008; +0170 : 80fdf008; 0171 : 5285aad5; 0172 : aad5720c; 0173 : 82800a53; @@ -390,10 +390,10 @@ 017b : 3f853d0d; 017c : 04fd3d0d; 017d : 800b80fd; -017e : ac085353; +017e : ec085353; 017f : ff87c3e1; 0180 : f0720c80; -0181 : fdb00873; +0181 : fdf00873; 0182 : 710c528c; 0183 : 9ac051fd; 0184 : a33f8880; @@ -402,10 +402,10 @@ 0187 : 34728184; 0188 : 80802e09; 0189 : 8106ef38; -018a : 80fdac08; +018a : 80fdec08; 018b : 5485aad5; 018c : aad5740c; -018d : 80fdb008; +018d : 80fdf008; 018e : 5285aad5; 018f : aad5720c; 0190 : 82800a53; @@ -419,8 +419,8 @@ 0198 : 8c9ac051; 0199 : fcce3f85; 019a : 3d0d04ff; -019b : 3d0d80fd; -019c : c0087008; +019b : 3d0d80fe; +019c : 80087008; 019d : 52527381; 019e : 2e8b3870; 019f : 81800772; @@ -428,8 +428,8 @@ 01a1 : 0470feff; 01a2 : 06720c83; 01a3 : 3d0d04ff; -01a4 : 3d0d80fd; -01a5 : c0087008; +01a4 : 3d0d80fe; +01a5 : 80087008; 01a6 : 5252738b; 01a7 : 3870ffbf; 01a8 : 06720c83; @@ -438,10 +438,10 @@ 01ab : 0c833d0d; 01ac : 04ff0b83; 01ad : e0b00c80; -01ae : ceac3f80; -01af : d1b03f83; +01ae : cee33f80; +01af : d1e73f83; 01b0 : e08008f3; -01b1 : 3880d3f5; +01b1 : 3880d4ac; 01b2 : 3f800b83; 01b3 : e0800c04; 01b4 : 803d0d70; @@ -476,22 +476,22 @@ 01d1 : 3d238070; 01d2 : 7183e2e4; 01d3 : 0c0b0b80; -01d4 : f5f45357; -01d5 : 5880da88; +01d4 : f6ac5357; +01d5 : 5880dabf; 01d6 : 3f765180; -01d7 : da823f0b; -01d8 : 0b80fab4; -01d9 : 5180d9f8; +01d7 : dab93f0b; +01d8 : 0b80faf4; +01d9 : 5180daaf; 01da : 3f765180; -01db : c2ba3f83; +01db : c2f13f83; 01dc : e0800878; 01dd : 2e8f380b; -01de : 0b80f680; -01df : 5180d9e0; +01de : 0b80f6b8; +01df : 5180da97; 01e0 : 3f8a3d0d; 01e1 : 040b0b80; -01e2 : f6885180; -01e3 : d9d23f75; +01e2 : f6c05180; +01e3 : da893f75; 01e4 : 17703355; 01e5 : 5573802e; 01e6 : 80fd3873; @@ -530,12 +530,12 @@ 0207 : 8a3dfc05; 0208 : 53905283; 0209 : e2e85180; -020a : c2be3f89; +020a : c2f53f89; 020b : 3d225574; 020c : 902e8e38; 020d : 0b0b80f6; -020e : 8c5180d8; -020f : a33ffec1; +020e : c45180d8; +020f : da3ffec1; 0210 : 3983e2e8; 0211 : 51fd953f; 0212 : 83e2ea51; @@ -552,11 +552,11 @@ 021d : 2e82ce38; 021e : 7385962e; 021f : 8e380b0b; -0220 : 80f6a451; -0221 : 80d7d93f; +0220 : 80f6dc51; +0221 : 80d8903f; 0222 : fdf7390b; -0223 : 0b80f6b8; -0224 : 5180d7cc; +0223 : 0b80f6f0; +0224 : 5180d883; 0225 : 3f7483e3; 0226 : 900c83e2; 0227 : ec3383e2; @@ -568,20 +568,20 @@ 022d : 81387381; 022e : ff2681b8; 022f : 380b0b80; -0230 : f6c05180; -0231 : d79a3f83; +0230 : f6f85180; +0231 : d7d13f83; 0232 : e2ea3383; 0233 : e2eb3371; 0234 : 882b0752; -0235 : 5680d897; +0235 : 5680d8ce; 0236 : 3f0b0b80; -0237 : f6c45180; -0238 : d6fe3f81; +0237 : f6fc5180; +0238 : d7b53f81; 0239 : 0b83e2e4; 023a : 0c8a3d0d; 023b : 040b0b80; -023c : f6c85180; -023d : d6ea3f80; +023c : f7805180; +023d : d7a13f80; 023e : 0b83e390; 023f : 0c820b83; 0240 : e2e834ff; @@ -613,29 +613,29 @@ 025a : ec34ff80; 025b : 0b83e2ed; 025c : 34fea739; -025d : 0b0b80f6; -025e : d05180d5; -025f : e33ffc81; +025d : 0b0b80f7; +025e : 885180d6; +025f : 9a3ffc81; 0260 : 3983e2ea; 0261 : 3383e2eb; 0262 : 3371882b; 0263 : 075558ad; 0264 : 80742781; 0265 : f2380b0b; -0266 : 80f6e051; -0267 : 80d5c13f; +0266 : 80f79851; +0267 : 80d5f83f; 0268 : 83e2ea33; 0269 : 83e2eb33; 026a : 71882b07; 026b : 525680d6; -026c : be3f0b0b; -026d : 80f6c451; -026e : 80d5a53f; +026c : f53f0b0b; +026d : 80f6fc51; +026e : 80d5dc3f; 026f : 810b83e2; 0270 : e40cfea5; 0271 : 390b0b80; -0272 : f6e45180; -0273 : d5923ffe; +0272 : f79c5180; +0273 : d5c93ffe; 0274 : 800b83e3; 0275 : 900c810b; 0276 : 83e3880c; @@ -682,43 +682,43 @@ 029f : 800b83e2; 02a0 : ed348055; 02a1 : ffa5390b; -02a2 : 0b80f6ec; -02a3 : 5180d3d0; +02a2 : 0b80f7a4; +02a3 : 5180d487; 02a4 : 3f83e2ea; 02a5 : 3383e2eb; 02a6 : 3371882b; 02a7 : 07525680; -02a8 : d4cd3f0b; -02a9 : 0b80f6c4; -02aa : 5180d3b4; +02a8 : d5843f0b; +02a9 : 0b80f6fc; +02aa : 5180d3eb; 02ab : 3f810b83; 02ac : e2e40cfc; 02ad : b4390b0b; -02ae : 80f6f051; -02af : 80d3a13f; +02ae : 80f7a851; +02af : 80d3d83f; 02b0 : 83e2ea33; 02b1 : 83e2eb33; 02b2 : 71882b07; 02b3 : 525680d4; -02b4 : 9e3f0b0b; -02b5 : 80f6c451; -02b6 : 80d3853f; +02b4 : d53f0b0b; +02b5 : 80f6fc51; +02b6 : 80d3bc3f; 02b7 : 810b83e2; 02b8 : e40cfc85; 02b9 : 39f73d0d; 02ba : 7b5a8c9a; 02bb : c051f3c4; 02bc : 3f805780; -02bd : d0c13f76; +02bd : d0f83f76; 02be : 54800b86; 02bf : b8c01534; 02c0 : 81145473; 02c1 : 87c02e09; 02c2 : 8106ee38; -02c3 : 0b0b80f5; -02c4 : f05283e2; -02c5 : f45180c0; -02c6 : f33f83e0; +02c3 : 0b0b80f6; +02c4 : a85283e2; +02c5 : f45180c1; +02c6 : aa3f83e0; 02c7 : 800883db; 02c8 : 38807083; 02c9 : e3a80855; @@ -728,8 +728,8 @@ 02cd : 80732482; 02ce : ff3883e0; 02cf : 945283e2; -02d0 : f45180c1; -02d1 : da3f83e0; +02d0 : f45180c2; +02d1 : 913f83e0; 02d2 : 800880db; 02d3 : 3883e09d; 02d4 : 33537280; @@ -751,17 +751,17 @@ 02e4 : 175783e0; 02e5 : 945283e2; 02e6 : f45180c1; -02e7 : 823f83e0; +02e7 : b93f83e0; 02e8 : 8008802e; 02e9 : ffa7380b; -02ea : 0b80fac0; -02eb : 5180d1b0; +02ea : 0b80fb80; +02eb : 5180d1e7; 02ec : 3f955180; -02ed : cf943f80; +02ed : cfcb3f80; 02ee : 0b83e0b4; 02ef : 0c7951f6; -02f0 : fb3f80fc; -02f1 : c0087033; +02f0 : fb3f80fd; +02f1 : 80087033; 02f2 : 7081ff06; 02f3 : 70812a81; 02f4 : 32708106; @@ -777,17 +777,17 @@ 02fe : 822a8132; 02ff : 70810651; 0300 : 537282a3; -0301 : 3880fcb8; +0301 : 3880fcf8; 0302 : 08703370; 0303 : 81ff0651; 0304 : 54547280; 0305 : 2e81f038; -0306 : 80ce9c3f; -0307 : 80fcc408; -0308 : 80fcd408; +0306 : 80ced33f; +0307 : 80fd8408; +0308 : 80fd9408; 0309 : 54547333; -030a : 733480fc; -030b : c0087033; +030a : 733480fd; +030b : 80087033; 030c : 7081ff06; 030d : 70812a81; 030e : 32708106; @@ -798,8 +798,8 @@ 0313 : 0583e3a8; 0314 : 0c84f180; 0315 : 51f0dd3f; -0316 : 805780cd; -0317 : da3f7654; +0316 : 805780ce; +0317 : 913f7654; 0318 : fd973974; 0319 : 83e09d57; 031a : 54731a53; @@ -816,8 +816,8 @@ 0325 : ff185877; 0326 : 8025fdf3; 0327 : 38a2390b; -0328 : 0b80f6f4; -0329 : 5180cfb8; +0328 : 0b80f7ac; +0329 : 5180cfef; 032a : 3f83e3a8; 032b : 08772e09; 032c : 8106fdd2; @@ -825,22 +825,22 @@ 032e : 7883e3a8; 032f : 0cfcfb39; 0330 : 83e09d51; -0331 : 80cf993f; +0331 : 80cfd03f; 0332 : 81197081; 0333 : 06545972; 0334 : 802e9338; -0335 : 945180cc; -0336 : eb3f78a8; +0335 : 945180cd; +0336 : a23f78a8; 0337 : 2efdc838; 0338 : 811757fd; 0339 : ad390b0b; -033a : 80fac051; -033b : 80cef13f; +033a : 80fb8051; +033b : 80cfa83f; 033c : 78a82e09; 033d : 8106e938; 033e : fdad390b; -033f : 0b80f6fc; -0340 : 5180cedc; +033f : 0b80f7b4; +0340 : 5180cf93; 0341 : 3fff3973; 0342 : 337081ff; 0343 : 06515372; @@ -864,7 +864,7 @@ 0355 : f18051fd; 0356 : fc39e23d; 0357 : 0d800b80; -0358 : fdb40870; +0358 : fdf40870; 0359 : 08708106; 035a : 51565658; 035b : 73782e09; @@ -880,13 +880,13 @@ 0365 : 8051f1d3; 0366 : 3f8151f1; 0367 : ce3f80fd; -0368 : b4085574; +0368 : f4085574; 0369 : 0870832a; 036a : 70810651; 036b : 51547380; 036c : 2e963880; 036d : 51f1b43f; -036e : 80fce008; +036e : 80fda008; 036f : 54807434; 0370 : f0af3f81; 0371 : 51f1a43f; @@ -894,60 +894,60 @@ 0373 : 8151f1bf; 0374 : 3ff09e3f; 0375 : 8e3d57a1; -0376 : 5380f5a8; +0376 : 5380f5e0; 0377 : 52765180; -0378 : d89a3f80; +0378 : d8d13f80; 0379 : 56848c80; 037a : 16761855; 037b : 55733375; 037c : 34811656; 037d : 75a12e09; 037e : 8106ea38; -037f : 80fcdc08; +037f : 80fd9c08; 0380 : 54807434; -0381 : 80fcd808; +0381 : 80fd9808; 0382 : 54867434; -0383 : 80fcd408; +0383 : 80fd9408; 0384 : 54807434; -0385 : 80fcd008; +0385 : 80fd9008; 0386 : 548f7434; -0387 : 80fccc08; +0387 : 80fd8c08; 0388 : 54807434; -0389 : 80fcc808; +0389 : 80fd8808; 038a : 54807434; -038b : 80fcbc08; +038b : 80fcfc08; 038c : 54ff7434; -038d : 80fcb408; +038d : 80fcf408; 038e : 54e07434; -038f : 80fcac08; +038f : 80fcec08; 0390 : 54a27434; 0391 : 815180ca; -0392 : 873f83e3; +0392 : be3f83e3; 0393 : 9851f995; 0394 : 3f83e080; 0395 : 08802ead; 0396 : 38810b83; 0397 : e0b40c0b; -0398 : 0b80f78c; -0399 : 5180cbf8; +0398 : 0b80f7c4; +0399 : 5180ccaf; 039a : 3f9ec2a0; 039b : 51ecc53f; 039c : 8051eff7; -039d : 3f80fce0; +039d : 3f80fda0; 039e : 08548074; 039f : 34eef23f; 03a0 : 8151efe7; 03a1 : 3f83e0ac; 03a2 : 085180c9; -03a3 : c33f8051; +03a3 : fa3f8051; 03a4 : effd3f80; -03a5 : fdb40855; +03a5 : fdf40855; 03a6 : fdea3977; 03a7 : 78797a5f; 03a8 : 595a5b81; 03a9 : 51efe83f; 03aa : 815180c9; -03ab : a33f819f; +03ab : da3f84df; 03ac : e0801886; 03ad : b8801955; 03ae : 55733375; @@ -961,7 +961,7 @@ 03b6 : 88802e09; 03b7 : 8106ed38; 03b8 : 83a08058; -03b9 : 819c8080; +03b9 : 84dc8080; 03ba : 18888080; 03bb : 19565474; 03bc : 33743484; @@ -971,7 +971,7 @@ 03c0 : a09f2e09; 03c1 : 8106dd38; 03c2 : 83a48058; -03c3 : 819c8080; +03c3 : 84dc8080; 03c4 : 18888080; 03c5 : 19565474; 03c6 : 33743484; @@ -981,7 +981,7 @@ 03ca : a49f2e09; 03cb : 8106dd38; 03cc : 83a88058; -03cd : 819c8080; +03cd : 84dc8080; 03ce : 18888080; 03cf : 19565474; 03d0 : 33743484; @@ -990,59 +990,59 @@ 03d3 : 18587783; 03d4 : a88f2e09; 03d5 : 8106dd38; -03d6 : 80fcbc08; +03d6 : 80fcfc08; 03d7 : 70337081; 03d8 : ff069a3d; 03d9 : 595c5154; -03da : a15380f5; -03db : cc527551; -03dc : 80d5893f; +03da : a15380f6; +03db : 84527551; +03dc : 80d5c03f; 03dd : 805886b8; 03de : 80187817; 03df : 55557333; 03e0 : 75348118; 03e1 : 5877a12e; 03e2 : 098106ea; -03e3 : 3880fcdc; +03e3 : 3880fd9c; 03e4 : 08548074; -03e5 : 3480fcd8; +03e5 : 3480fd98; 03e6 : 0854ff9c; -03e7 : 743480fc; -03e8 : d4085480; -03e9 : 743480fc; -03ea : d008548f; -03eb : 743480fc; -03ec : cc085480; -03ed : 743480fc; -03ee : c8085480; +03e7 : 743480fd; +03e8 : 94085480; +03e9 : 743480fd; +03ea : 9008548f; +03eb : 743480fd; +03ec : 8c085480; +03ed : 743480fd; +03ee : 88085480; 03ef : 743480fc; -03f0 : b40854e0; +03f0 : f40854e0; 03f1 : 743480fc; -03f2 : ac0854a2; +03f2 : ec0854a2; 03f3 : 743480fc; -03f4 : bc0854ff; +03f4 : fc0854ff; 03f5 : 743480fc; -03f6 : a8085483; +03f6 : e8085483; 03f7 : 743480fc; -03f8 : b0085482; +03f8 : f0085482; 03f9 : 7434fd5d; 03fa : 87a9c051; 03fb : e9c63f80; -03fc : c6c53f80; +03fc : c6fc3f80; 03fd : 58800b86; 03fe : b8c01934; 03ff : 81185877; 0400 : 87c02e09; 0401 : 8106ee38; 0402 : 0b0b80f7; -0403 : 985180c8; -0404 : cf3f0b0b; -0405 : 80f7ac51; -0406 : 80c8c53f; +0403 : d05180c9; +0404 : 863f0b0b; +0405 : 80f7e451; +0406 : 80c8fc3f; 0407 : 0b0b80f7; -0408 : c05180c8; -0409 : bb3f80fd; -040a : c0087008; +0408 : f85180c8; +0409 : f23f80fe; +040a : 80087008; 040b : 70882c8f; 040c : 06575556; 040d : 78b33876; @@ -1054,25 +1054,25 @@ 0413 : 7a7b5a5e; 0414 : 565487a9; 0415 : c051e8dc; -0416 : 3f80c5db; +0416 : 3f80c692; 0417 : 3f8058ff; 0418 : 94398180; -0419 : 5180c7f2; +0419 : 5180c8a9; 041a : 3f74812e; -041b : 89983881; -041c : 752588d9; +041b : 899c3881; +041c : 752588dd; 041d : 3874822e; -041e : 88903874; +041e : 88933874; 041f : 832e869b; 0420 : 380b0b80; -0421 : f7c85180; -0422 : c7d63f0b; -0423 : 0b80fac0; -0424 : 5180c7cc; +0421 : f8805180; +0422 : c88d3f0b; +0423 : 0b80fb80; +0424 : 5180c883; 0425 : 3f0b0b80; -0426 : f7d05180; -0427 : c7c23f80; -0428 : fdc00870; +0426 : f8885180; +0427 : c7f93f80; +0428 : fe800870; 0429 : 08708c2c; 042a : 8f065755; 042b : 5678812e; @@ -1080,17 +1080,17 @@ 042d : 812e87a1; 042e : 38817525; 042f : 86e33874; -0430 : 822e8cae; +0430 : 822e8cb2; 0431 : 3874832e; -0432 : 8ce7380b; -0433 : 0b80f7c8; -0434 : 5180c78c; +0432 : 8ceb380b; +0433 : 0b80f880; +0434 : 5180c7c3; 0435 : 3f0b0b80; -0436 : fac05180; -0437 : c7823f0b; -0438 : 0b80f7dc; -0439 : 5180c6f8; -043a : 3f80fdc0; +0436 : fb805180; +0437 : c7b93f0b; +0438 : 0b80f894; +0439 : 5180c7af; +043a : 3f80fe80; 043b : 087008bf; 043c : 06565678; 043d : 822e8680; @@ -1098,49 +1098,49 @@ 043f : 83c19c35; 0440 : 7083ffff; 0441 : 06535154; -0442 : 80c7e43f; -0443 : 0b0b80f7; -0444 : e45180c6; -0445 : cb3f7883; +0442 : 80c89b3f; +0443 : 0b0b80f8; +0444 : 9c5180c7; +0445 : 823f7883; 0446 : 2e85b838; 0447 : 83e39851; -0448 : 80c6bd3f; -0449 : 0b0b80f7; -044a : f05180c6; -044b : b33f7884; +0448 : 80c6f43f; +0449 : 0b0b80f8; +044a : a85180c6; +044b : ea3f7884; 044c : 2e84c338; 044d : 83e3d851; -044e : 80c6a53f; -044f : 0b0b80f7; -0450 : f85180c6; -0451 : 9b3f7885; +044e : 80c6dc3f; +044f : 0b0b80f8; +0450 : b05180c6; +0451 : d23f7885; 0452 : 2e848638; 0453 : 83e2c851; -0454 : 80c68d3f; +0454 : 80c6c43f; 0455 : 0b0b80f8; -0456 : 805180c6; -0457 : 833f7886; +0456 : b85180c6; +0457 : ba3f7886; 0458 : 2e85b438; 0459 : 83e0b851; -045a : 80c5f53f; +045a : 80c6ac3f; 045b : 7c832693; 045c : 387b812e; -045d : 87c53876; -045e : 812e8a90; +045d : 87c93876; +045e : 812e8a94; 045f : 3876ff2e; -0460 : 89a43878; -0461 : 872e88a0; +0460 : 89a83878; +0461 : 872e88a4; 0462 : 380b0b80; -0463 : f8885180; -0464 : c5ce3f78; -0465 : 872e86a7; +0463 : f8c05180; +0464 : c6853f78; +0465 : 872e86ab; 0466 : 3878882e; -0467 : 8893380b; -0468 : 0b80f890; -0469 : 5180c5b8; +0467 : 8897380b; +0468 : 0b80f8c8; +0469 : 5180c5ef; 046a : 3f78882e; 046b : 81d33880; -046c : 7080fcc0; +046c : 7080fd80; 046d : 08703370; 046e : 81ff0670; 046f : 812a8132; @@ -1149,24 +1149,24 @@ 0472 : 7580e938; 0473 : 74813270; 0474 : 81065154; -0475 : 7388b538; +0475 : 7388b938; 0476 : 74832a81; 0477 : 32708106; 0478 : 51547388; -0479 : 96387482; +0479 : 9a387482; 047a : 2a813270; 047b : 81065154; -047c : 7387f738; -047d : 80fcb808; +047c : 7387fb38; +047d : 80fcf808; 047e : 70337081; 047f : ff065155; 0480 : 5573802e; -0481 : 87c63880; -0482 : c2ad3f80; -0483 : fcc40880; -0484 : fcd40855; +0481 : 87ca3880; +0482 : c2e43f80; +0483 : fd840880; +0484 : fd940855; 0485 : 55743374; -0486 : 3480fcc0; +0486 : 3480fd80; 0487 : 08703370; 0488 : 81ff0670; 0489 : 812a8132; @@ -1179,10 +1179,10 @@ 0490 : 8859855d; 0491 : 87a9c051; 0492 : e4ea3f80; -0493 : c1e93f80; +0493 : c2a03f80; 0494 : 58fba239; 0495 : 76802e87; -0496 : c4387508; +0496 : c8387508; 0497 : 77168306; 0498 : 71fc9fff; 0499 : 06718c2b; @@ -1190,13 +1190,13 @@ 049b : 54807058; 049c : 5c87a9c0; 049d : 51e4bd3f; -049e : 80c1bc3f; +049e : 80c1f33f; 049f : 8058faf5; 04a0 : 397b812e; 04a1 : 098106fe; 04a2 : a63880c0; 04a3 : 5886b880; -04a4 : 18819fe0; +04a4 : 1884dfe0; 04a5 : 80195555; 04a6 : 73337534; 04a7 : 81185877; @@ -1204,7 +1204,7 @@ 04a9 : 8106e638; 04aa : 83a08058; 04ab : 84808018; -04ac : 819c8080; +04ac : 84dc8080; 04ad : 19555573; 04ae : 33753481; 04af : 18587783; @@ -1212,7 +1212,7 @@ 04b1 : 8106e538; 04b2 : 83a48058; 04b3 : 84808018; -04b4 : 819c8080; +04b4 : 84dc8080; 04b5 : 19555573; 04b6 : 33753481; 04b7 : 18587783; @@ -1220,57 +1220,57 @@ 04b9 : 8106e538; 04ba : 83a88058; 04bb : 84808018; -04bc : 819c8080; +04bc : 84dc8080; 04bd : 19555573; 04be : 33753481; 04bf : 18587783; 04c0 : a88f2e09; 04c1 : 8106e538; -04c2 : 80fcbc08; +04c2 : 80fcfc08; 04c3 : 54797434; 04c4 : 83e0ac08; -04c5 : 5180c0b8; +04c5 : 5180c0ef; 04c6 : 3f7a802e; 04c7 : a7380b0b; -04c8 : 80f78c51; -04c9 : 80c2b93f; +04c8 : 80f7c451; +04c9 : 80c2f03f; 04ca : 9ec2a051; 04cb : e3863f80; 04cc : 51e6b83f; -04cd : 80fce008; +04cd : 80fda008; 04ce : 54807434; 04cf : e5b33f81; 04d0 : 51e6a83f; 04d1 : 8051e6c7; -04d2 : 3f80fdb4; +04d2 : 3f80fdf4; 04d3 : 0855f4a5; 04d4 : 39818051; -04d5 : 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+0fa0 : 0001d300; +0fa1 : 0001d20a; +0fa2 : 0001d01b; +0fa3 : 0001d018; +0fa4 : 0001d017; +0fa5 : 0001d01a; +0fa6 : 0001d403; +0fa7 : 0001d402; +0fa8 : 0001d40e; +0fa9 : 0004007c; +0faa : 00040078; +0fab : 00040074; +0fac : 00040068; +0fad : 00040060; +0fae : 0004005c; +0faf : 00040058; +0fb0 : 00040054; +0fb1 : 00040050; +0fb2 : 0004004c; +0fb3 : 00040048; +0fb4 : 00040044; +0fb5 : 00040040; +0fb6 : 00040028; +0fb7 : 00040024; +0fb8 : 00040020; +0fb9 : 0004001c; +0fba : 00040018; +0fbb : 00040014; +0fbc : 00040010; +0fbd : 0004000c; +0fbe : 00040008; +0fbf : 00040004; +0fc0 : 00040000; END; diff -ur atari800core_20140301_de1/zpu_config_regs.vhdl atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl --- atari800core_20140301_de1/zpu_config_regs.vhdl 2014-01-18 20:59:03.000000000 +0000 +++ atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl 2014-02-02 19:12:56.000000000 +0000 @@ -413,11 +413,11 @@ end if; if (addr_decoded(2) = '1') then - data_out(9 downto 0) <= SWITCH; + data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD. end if; if (addr_decoded(3) = '1') then - data_out(3 downto 0) <= KEY; + data_out(3 downto 0) <= key; end if; if (addr_decoded(4) = '1') then @@ -441,11 +441,11 @@ end if; if (addr_decoded(9) = '1') then - data_out <= X"00000000"; -- DE1! + --data_out <= X"00000000"; -- DE1! --data_out <= X"00000001"; -- DE2! --data_out <= X"00000002"; -- SOCKIT! --data_out <= X"00000003"; -- REPLAY! - --data_out <= X"00000004"; -- MMC! + data_out <= X"00000004"; -- MMC! end if; if (addr_decoded(10) = '1') then @@ -479,12 +479,12 @@ spi_miso <= SDCARD_DAT; -- INPUT!! XXX SDCARD_DAT3 <= spi_chip_select(0); - PAL <= switch(6); - USE_SDRAM <= switch(7); -- should not be all or nothing. can mix for higher ram settings... + PAL <= '1'; -- TODO + USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings... RAM_SELECT <= ram_select_reg; - VGA <= switch(9); - COMPOSITE_ON_HSYNC <= switch(8); - GPIO_ENABLE <= gpio_enable_reg; -- enable gpio - FIXME - esp carts! + VGA <= '1'; + COMPOSITE_ON_HSYNC <= '0'; + GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts! ROM_SELECT <= rom_select_reg; reset_n <= reset_n_reg; -- system reset or pll not locked