TimeQuest Timing Analyzer report for atari800core
Thu Aug 21 07:29:22 2014
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 16. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 18. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 19. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 21. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 23. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 24. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 25. Setup Times
 26. Hold Times
 27. Clock to Output Times
 28. Minimum Clock to Output Times
 29. Output Enable Times
 30. Minimum Output Enable Times
 31. Output Disable Times
 32. Minimum Output Disable Times
 33. Slow 1200mV 85C Model Metastability Report
 34. Slow 1200mV 0C Model Fmax Summary
 35. Slow 1200mV 0C Model Setup Summary
 36. Slow 1200mV 0C Model Hold Summary
 37. Slow 1200mV 0C Model Recovery Summary
 38. Slow 1200mV 0C Model Removal Summary
 39. Slow 1200mV 0C Model Minimum Pulse Width Summary
 40. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 42. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 43. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 44. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 45. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 46. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 47. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 48. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 49. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 50. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 51. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 52. Setup Times
 53. Hold Times
 54. Clock to Output Times
 55. Minimum Clock to Output Times
 56. Output Enable Times
 57. Minimum Output Enable Times
 58. Output Disable Times
 59. Minimum Output Disable Times
 60. Slow 1200mV 0C Model Metastability Report
 61. Fast 1200mV 0C Model Setup Summary
 62. Fast 1200mV 0C Model Hold Summary
 63. Fast 1200mV 0C Model Recovery Summary
 64. Fast 1200mV 0C Model Removal Summary
 65. Fast 1200mV 0C Model Minimum Pulse Width Summary
 66. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 68. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 69. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 70. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 71. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 72. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 74. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 75. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 76. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 77. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 78. Setup Times
 79. Hold Times
 80. Clock to Output Times
 81. Minimum Clock to Output Times
 82. Output Enable Times
 83. Minimum Output Enable Times
 84. Output Disable Times
 85. Minimum Output Disable Times
 86. Fast 1200mV 0C Model Metastability Report
 87. Multicorner Timing Analysis Summary
 88. Setup Times
 89. Hold Times
 90. Clock to Output Times
 91. Minimum Clock to Output Times
 92. Board Trace Model Assignments
 93. Input Transition Times
 94. Slow Corner Signal Integrity Metrics
 95. Fast Corner Signal Integrity Metrics
 96. Setup Transfers
 97. Hold Transfers
 98. Recovery Transfers
 99. Removal Transfers
100. Report TCCS
101. Report RSKM
102. Unconstrained Paths
103. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.35        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  35.0%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Thu Aug 21 07:29:03 2014 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; Clock Name                                                                    ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                       ; Source                                                                          ; Targets                                                                           ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz ; 7.635 ; 13.508  ; 50.00      ; 1         ; 3           ; 234.0 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                      ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                              ;                                                                                 ; { FPGA_CLK }                                                                      ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 43.39 MHz  ; 43.39 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 129.45 MHz ; 129.45 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                   ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.110 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.076 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                    ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.415 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.454 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.186 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.594 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                 ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.763 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.020 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                      ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.571  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.320 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.584 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.862 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                     ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                     ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.110 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 11.311     ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 11.253     ;
; 0.237 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 11.183     ;
; 0.261 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 11.160     ;
; 0.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 11.102     ;
; 0.366 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 11.055     ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 11.032     ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 10.992     ;
; 0.422 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.997     ;
; 0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.980     ;
; 0.446 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.207     ; 10.965     ;
; 0.456 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.951     ;
; 0.493 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.927     ;
; 0.497 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 10.924     ;
; 0.502 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 10.907     ;
; 0.530 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 10.878     ;
; 0.553 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.866     ;
; 0.573 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 10.837     ;
; 0.579 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 10.830     ;
; 0.586 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.820     ;
; 0.591 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.829     ;
; 0.624 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.796     ;
; 0.631 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 10.790     ;
; 0.657 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.750     ;
; 0.663 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.744     ;
; 0.676 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.744     ;
; 0.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 10.731     ;
; 0.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.732     ;
; 0.688 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 10.720     ;
; 0.689 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.731     ;
; 0.696 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.724     ;
; 0.709 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 10.709     ;
; 0.741 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.678     ;
; 0.749 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 10.681     ;
; 0.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.651     ;
; 0.758 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.662     ;
; 0.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 10.634     ;
; 0.792 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.640     ;
; 0.827 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.593     ;
; 0.860 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.547     ;
; 0.867 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 10.525     ;
; 0.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 10.537     ;
; 0.892 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.527     ;
; 0.901 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 10.508     ;
; 0.916 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.504     ;
; 0.920 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.486     ;
; 0.939 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.468     ;
; 0.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.450     ;
; 0.961 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.459     ;
; 0.972 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 10.446     ;
; 0.997 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.422     ;
; 1.010 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 10.398     ;
; 1.011 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.396     ;
; 1.028 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 10.380     ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.372     ;
; 1.043 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.376     ;
; 1.053 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 10.365     ;
; 1.058 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[6]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.374     ;
; 1.076 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 10.318     ;
; 1.077 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 10.332     ;
; 1.096 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.324     ;
; 1.107 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.312     ;
; 1.114 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.292     ;
; 1.117 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.289     ;
; 1.119 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.287     ;
; 1.120 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.299     ;
; 1.127 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 10.282     ;
; 1.128 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.291     ;
; 1.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 10.264     ;
; 1.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.282     ;
; 1.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.245     ;
; 1.163 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 10.242     ;
; 1.200 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 10.230     ;
; 1.203 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.204     ;
; 1.203 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 10.204     ;
; 1.203 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 10.214     ;
; 1.231 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 10.177     ;
; 1.246 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.173     ;
; 1.248 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.158     ;
; 1.262 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 10.157     ;
; 1.268 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.138     ;
; 1.279 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 10.146     ;
; 1.282 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 10.111     ;
; 1.288 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.118     ;
; 1.316 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 10.115     ;
; 1.339 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 10.082     ;
; 1.339 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 10.053     ;
; 1.342 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 10.078     ;
; 1.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 10.049     ;
; 1.373 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 10.033     ;
; 1.408 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 9.999      ;
; 1.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[6]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 10.014     ;
; 1.424 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 9.981      ;
; 1.428 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 9.992      ;
; 1.439 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 9.967      ;
; 1.452 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 9.968      ;
; 1.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.222     ; 9.943      ;
; 1.459 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 9.949      ;
; 1.468 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 9.954      ;
; 1.468 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 9.954      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                             ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.076 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[5]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.474      ;
; 2.076 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.474      ;
; 2.164 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 9.383      ;
; 2.210 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 9.366      ;
; 2.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 9.187      ;
; 2.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 9.187      ;
; 2.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 9.187      ;
; 2.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 9.187      ;
; 2.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 9.187      ;
; 2.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 9.187      ;
; 2.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 9.187      ;
; 2.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 9.187      ;
; 2.429 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 9.119      ;
; 2.429 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 9.119      ;
; 2.429 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 9.119      ;
; 2.429 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 9.119      ;
; 2.429 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 9.119      ;
; 2.429 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 9.119      ;
; 2.429 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 9.119      ;
; 2.429 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 9.119      ;
; 2.434 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 9.140      ;
; 2.536 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 9.011      ;
; 2.536 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[7]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 9.011      ;
; 2.536 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[2]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 9.011      ;
; 2.536 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[0]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 9.011      ;
; 2.536 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[1]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 9.011      ;
; 2.536 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[3]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 9.011      ;
; 2.545 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 9.028      ;
; 2.572 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 9.006      ;
; 2.590 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.955      ;
; 2.624 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 8.954      ;
; 2.673 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.903      ;
; 2.675 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.901      ;
; 2.680 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.896      ;
; 2.681 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 8.897      ;
; 2.704 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.843      ;
; 2.704 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.843      ;
; 2.704 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.843      ;
; 2.704 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.843      ;
; 2.704 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.843      ;
; 2.704 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.843      ;
; 2.704 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.843      ;
; 2.704 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.843      ;
; 2.778 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 8.801      ;
; 2.792 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 8.787      ;
; 2.792 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 8.786      ;
; 2.795 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.750      ;
; 2.795 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.750      ;
; 2.795 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.750      ;
; 2.795 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.750      ;
; 2.795 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.750      ;
; 2.795 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.750      ;
; 2.795 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.750      ;
; 2.795 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.750      ;
; 2.853 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.723      ;
; 2.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 8.687      ;
; 2.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 8.702      ;
; 2.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 8.702      ;
; 2.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 8.702      ;
; 2.869 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.677      ;
; 2.869 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.677      ;
; 2.869 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.677      ;
; 2.869 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.677      ;
; 2.869 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.677      ;
; 2.869 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.677      ;
; 2.875 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.701      ;
; 2.881 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.665      ;
; 2.881 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.665      ;
; 2.881 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.665      ;
; 2.881 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.665      ;
; 2.881 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.665      ;
; 2.881 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.665      ;
; 2.881 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.665      ;
; 2.881 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.665      ;
; 2.890 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 8.671      ;
; 2.892 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.681      ;
; 2.899 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.674      ;
; 2.901 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.671      ;
; 2.901 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.671      ;
; 2.901 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.671      ;
; 2.907 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.663      ;
; 2.907 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.663      ;
; 2.926 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.654      ;
; 2.935 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.637      ;
; 2.951 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.625      ;
; 2.955 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.625      ;
; 2.963 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.586      ;
; 3.002 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.578      ;
; 3.011 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.561      ;
; 3.025 ; ram_do_reg[6]              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.539      ;
; 3.029 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.543      ;
; 3.038 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.538      ;
; 3.043 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.533      ;
; 3.088 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 8.488      ;
; 3.144 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.402      ;
; 3.144 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.402      ;
; 3.144 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.402      ;
; 3.144 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.402      ;
; 3.144 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.402      ;
; 3.144 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.203     ; 8.402      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                   ; To Node                                                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.415 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                                   ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.148      ;
; 0.415 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                                   ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.148      ;
; 0.447 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                   ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.180      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[7]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[7]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.811      ;
; 0.537 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.828      ;
; 0.699 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.990      ;
; 0.725 ; sdram_ctrl:sdram_controller|r_wr_reg                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.016      ;
; 0.735 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.026      ;
; 0.736 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.027      ;
; 0.736 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.027      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.741 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.743 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.744 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.035      ;
; 0.745 ; ram_bena_reg[0]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.036      ;
; 0.746 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.037      ;
; 0.746 ; ram_bena_reg[1]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.037      ;
; 0.753 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.043      ;
; 0.758 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.049      ;
; 0.778 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.070      ;
; 0.800 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.091      ;
; 0.816 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.107      ;
; 0.816 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.107      ;
; 0.867 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.158      ;
; 0.893 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.301      ;
; 0.912 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.203      ;
; 0.929 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.221      ;
; 0.948 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.240      ;
; 0.951 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.242      ;
; 0.960 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.251      ;
; 0.960 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.251      ;
; 0.963 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.254      ;
; 0.977 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.385      ;
; 0.978 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.269      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.386      ;
; 0.979 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.387      ;
; 0.983 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.274      ;
; 0.985 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.393      ;
; 0.985 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 1.394      ;
; 0.986 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.394      ;
; 0.986 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 1.395      ;
; 0.987 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.395      ;
; 0.990 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 1.399      ;
; 0.991 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 1.400      ;
; 0.991 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 1.400      ;
; 0.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.400      ;
; 0.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.403      ;
; 0.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.403      ;
; 0.998 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.289      ;
; 1.001 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.291      ;
; 1.003 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.293      ;
; 1.004 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[13]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.412      ;
; 1.004 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.412      ;
; 1.008 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[15]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.416      ;
; 1.011 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[12]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.419      ;
; 1.014 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.305      ;
; 1.014 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.422      ;
; 1.015 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.423      ;
; 1.016 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.424      ;
; 1.017 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.425      ;
; 1.017 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.425      ;
; 1.018 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 1.426      ;
; 1.035 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.326      ;
; 1.043 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.334      ;
; 1.060 ; seq_reg[4]                                                                                                      ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.352      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[26]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.480      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[19]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.480      ;
; 1.076 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[25]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.483      ;
; 1.079 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[21]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.486      ;
; 1.081 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[30]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.488      ;
; 1.083 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[24]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.490      ;
; 1.084 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[18]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.491      ;
; 1.085 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[29]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.492      ;
; 1.085 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[28]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.492      ;
; 1.085 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[17]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.492      ;
; 1.086 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[27]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.493      ;
; 1.087 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[31]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.494      ;
; 1.088 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[22]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.495      ;
; 1.088 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[23]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.495      ;
; 1.089 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[20]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 1.496      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.382      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.382      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.384      ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                             ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                            ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot0_reg[7]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot0_reg[3]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot0_reg[2]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.186 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot0_reg[6]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.387      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 6.380      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 6.371      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.189     ; 6.373      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 6.389      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.386      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 6.367      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 6.367      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 6.374      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 6.368      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 6.368      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 6.370      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 6.370      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 6.370      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 6.370      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 6.387      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 6.379      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 6.371      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 6.384      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 6.371      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 6.370      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 6.370      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 6.384      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 6.375      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[25]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 6.379      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 6.379      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 6.368      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 6.368      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 6.368      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 6.368      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 6.368      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 6.379      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 6.374      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 6.389      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 6.367      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[3]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[2]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[2]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.197     ; 6.365      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[3]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.197     ; 6.365      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[7]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[6]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[5]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 6.371      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[4]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 6.380      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 6.374      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[5]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 6.380      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.189     ; 6.373      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[0]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 6.381      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.197     ; 6.365      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 6.380      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 6.371      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[8]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 6.380      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 6.367      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[11]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[10]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 6.383      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.386      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.386      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.386      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.386      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.386      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.386      ;
; 5.187 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 6.386      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                     ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 7.594 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.406     ; 3.606      ;
; 7.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.393     ; 3.618      ;
; 7.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.405     ; 3.606      ;
; 7.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.405     ; 3.606      ;
; 7.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.405     ; 3.606      ;
; 7.598 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.404     ; 3.604      ;
; 7.600 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.410     ; 3.596      ;
; 7.600 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.408     ; 3.598      ;
; 7.601 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.794      ;
; 7.601 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.794      ;
; 7.601 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.794      ;
; 7.601 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.794      ;
; 7.603 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.792      ;
; 7.603 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 3.792      ;
; 7.604 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.221     ; 3.793      ;
; 7.612 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.266     ; 3.740      ;
; 7.613 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.278     ; 3.727      ;
; 7.613 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.278     ; 3.727      ;
; 7.613 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.278     ; 3.727      ;
; 7.614 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.279     ; 3.725      ;
; 7.618 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.396     ; 3.592      ;
; 7.618 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.396     ; 3.592      ;
; 7.618 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.396     ; 3.592      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.394     ; 3.593      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.394     ; 3.593      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.394     ; 3.593      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.281     ; 3.717      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.277     ; 3.721      ;
; 7.621 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.283     ; 3.714      ;
; 7.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.396     ; 3.588      ;
; 7.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.392     ; 3.592      ;
; 7.630 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.780      ;
; 7.630 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 3.779      ;
; 7.630 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 3.779      ;
; 7.631 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 3.778      ;
; 7.631 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 3.777      ;
; 7.631 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 3.777      ;
; 7.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.269     ; 3.710      ;
; 7.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.269     ; 3.710      ;
; 7.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.269     ; 3.710      ;
; 7.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.267     ; 3.712      ;
; 7.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.267     ; 3.712      ;
; 7.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.267     ; 3.712      ;
; 7.640 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.265     ; 3.713      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.877      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.877      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.877      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.877      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.269     ; 3.707      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.877      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.875      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.875      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.875      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.228     ; 3.876      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.228     ; 3.876      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.875      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.228     ; 3.876      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.875      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.228     ; 3.876      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.228     ; 3.876      ;
; 7.660 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.875      ;
; 7.853 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.221     ; 3.544      ;
; 7.853 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.221     ; 3.544      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.221     ; 3.543      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.221     ; 3.543      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.389      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.399      ;
; 8.148 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.399      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.396      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.396      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.396      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.396      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.385      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.385      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.401      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.163      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.161      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.161      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.161      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.161      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.161      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.161      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.161      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.161      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.175      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.175      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.175      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.175      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.166      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.177      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.177      ;
; 2.765 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.175      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.164      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.164      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.164      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.164      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.164      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.164      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.164      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.165      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.165      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.165      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.165      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.165      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.180      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.165      ;
; 2.766 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.165      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.165      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.165      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.166      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.166      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.166      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.165      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.165      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.165      ;
; 2.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.165      ;
; 2.996 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 3.305      ;
; 2.996 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 3.306      ;
; 2.996 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 3.306      ;
; 2.996 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 3.305      ;
; 3.223 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.622      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.620      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.620      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.620      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.620      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.620      ;
; 3.238 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.621      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                       ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 5.020 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[6]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.324      ;
; 5.020 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.323      ;
; 5.021 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[7]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.326      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[1]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[3]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[1]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[0][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[0][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[0][6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[0][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[2][1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 5.342      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 5.339      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[2]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 5.340      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[2][0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[0]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 5.338      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[4][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[3][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[2][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[1][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[0][1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[4][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[3][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[2][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
; 5.035 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[1][0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 5.341      ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                      ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][0]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][1]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][2]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][3]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][4]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][5]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][6]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][7]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][0]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][1]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][2]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][3]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][4]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][5]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][6]                    ;
; 17.320 ; 17.540       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][7]                    ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[10] ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[11] ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[12] ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[13] ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[14] ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[15] ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[4]                                       ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[7]                                       ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                          ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[0]  ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[1]  ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[2]  ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[3]  ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[4]  ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[5]  ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]                     ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                     ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                     ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                     ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                     ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processInt                      ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processIrq                      ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processNmi                      ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[10]                                                                                                           ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[11]                                                                                                           ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[12]                                                                                                           ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[2]                                                                                                            ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[3]                                                                                                            ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[4]                                                                                                            ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[5]                                                                                                            ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[6]                                                                                                            ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[7]                                                                                                            ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[8]                                                                                                            ;
; 17.321 ; 17.541       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[9]                                                                                                            ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                   ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|an_prev_reg[0]                                         ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|an_prev_reg[1]                                         ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|an_prev_reg[2]                                         ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[8]  ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[9]  ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[11]  ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[12]  ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[13]  ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[14]  ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[15]  ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[0]                                       ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[2]                                       ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[3]                                       ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[0]                              ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                              ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                              ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                              ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_display_shift_reg[10]                            ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_display_shift_reg[11]                            ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_display_shift_reg[15]                            ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_display_shift_reg[16]                            ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_display_shift_reg[20]                            ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_display_shift_reg[21]                            ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_display_shift_reg[5]                             ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_display_shift_reg[6]                             ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[0]                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[1]                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[2]                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[3]                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[4]                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[5]                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[6]                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[7]                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_shift_reg[1]                                   ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_shift_reg[2]                                   ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_shift_reg[3]                                   ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_shift_reg[4]                                   ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_shift_reg[5]                                   ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_shift_reg[6]                                   ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_shift_reg[7]                                   ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                     ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                    ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                     ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                     ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                     ;
; 17.322 ; 17.542       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                     ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.929  ; 99.929       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.070 ; 100.070      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.023 ; 3.130 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026 ; 3.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.724 ; 6.016 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.664 ; 4.962 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 3.956 ; 4.184 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.063 ; 4.288 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 3.830 ; 4.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 5.724 ; 6.016 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 5.528 ; 5.811 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.014 ; 4.171 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.109 ; 4.306 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.163 ; 4.409 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 3.959 ; 4.212 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 5.528 ; 5.811 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.933 ; 7.280 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.523 ; 6.772 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.056 ; 4.334 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.027 ; -2.134 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.045 ; -2.152 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.042 ; -2.149 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.039 ; -2.146 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.050 ; -2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.036 ; -2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.764 ; -2.997 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.498 ; -3.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.884 ; -3.096 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.905 ; -3.099 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.764 ; -2.997 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.070 ; -3.261 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.888 ; -3.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.936 ; -3.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -2.968 ; -3.126 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -3.050 ; -3.253 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.888 ; -3.123 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.101 ; -3.283 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.750 ; -6.086 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -5.363 ; -5.600 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.996 ; -3.268 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                       ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.389  ; 3.932  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.289  ; 3.000  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.284  ; 2.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.293  ; 3.004  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.302  ; 3.013  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.389  ; 3.932  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.303  ; 3.014  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.313  ; 3.024  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.289  ; 3.000  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.376  ; 3.919  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.290  ; 3.001  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.376  ; 3.919  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.388  ; 3.931  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.300  ; 3.011  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.450  ; 3.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.574  ; 3.263  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.574  ; 3.263  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.574  ; 3.263  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.443  ; 3.988  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.425  ; 3.970  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.356  ; 2.151  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.477  ; 3.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.486  ; 3.189  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.608  ; 3.297  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.450  ; 3.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.604  ; 3.293  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.604  ; 3.293  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.594  ; 3.283  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.442  ; 3.987  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.586  ; 3.275  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.596  ; 3.285  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.408  ; 4.793  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.436  ; 3.741  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.408  ; 4.793  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.300  ; 3.011  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.311  ; 3.022  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.641  ; 7.799  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.342  ; 4.197  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.150  ; 3.884  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.249  ; 6.470  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.037  ; 3.203  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 12.599 ; 12.840 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 9.303  ; 9.189  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 12.599 ; 12.840 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.458  ; 9.191  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 11.315 ; 11.817 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 11.734 ; 11.969 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 11.734 ; 11.969 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 9.417  ; 9.151  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.800  ; 8.523  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 8.116  ; 7.838  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 7.628  ; 7.486  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 8.882  ; 8.702  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.633  ; 8.367  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 8.607  ; 8.357  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 8.446  ; 8.243  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.882  ; 8.702  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.284  ; 2.160  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.086  ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 8.846  ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.422 ; 2.138 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.431 ; 2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.440 ; 2.156 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.573 ; 3.117 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.441 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.451 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.560 ; 3.104 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.572 ; 3.116 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.629 ; 3.175 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.612 ; 3.158 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.615 ; 2.324 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.623 ; 2.332 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.745 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.636 ; 3.182 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.731 ; 2.426 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.628 ; 3.174 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.723 ; 2.418 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.733 ; 2.428 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.569 ; 2.868 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.569 ; 2.868 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.502 ; 3.878 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.449 ; 2.165 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.734 ; 6.900 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.463 ; 3.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.265 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.390 ; 5.614 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.193 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 4.425 ; 4.324 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 4.425 ; 4.324 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 7.318 ; 7.461 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 4.586 ; 4.409 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 7.409 ; 7.592 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 4.052 ; 3.796 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 6.678 ; 6.926 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 4.052 ; 3.796 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 4.556 ; 4.258 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 4.536 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 6.463 ; 6.336 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 4.302 ; 4.106 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 4.302 ; 4.106 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 4.714 ; 4.549 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 4.512 ; 4.306 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 4.498 ; 4.267 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.468 ; 1.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.316 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.080 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.103 ; 3.103 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.511 ; 3.511 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.511 ; 3.511 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.511 ; 3.511 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.103 ; 3.103 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.540 ; 3.540 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.868 ; 3.868 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.939 ; 3.939 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.950 ; 3.950 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 5.275 ; 5.275 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.879 ; 4.879 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.393 ; 4.393 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.393 ; 4.393 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.383 ; 4.383 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.428 ; 4.428 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.418 ; 4.418 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.428 ; 4.428 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.059 ; 3.675 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.756 ; 1.785 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.147 ; 2.176 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.147 ; 2.176 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.147 ; 2.176 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.756 ; 1.785 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.176 ; 2.205 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.491 ; 2.520 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.558 ; 2.587 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.569 ; 2.598 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.841 ; 3.870 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.462 ; 3.491 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.995 ; 3.024 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.995 ; 3.024 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.985 ; 3.014 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.028 ; 3.057 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.018 ; 3.047 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.028 ; 3.057 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.081 ; 2.713 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.795     ; 3.035     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.177     ; 3.417     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.177     ; 3.417     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.177     ; 3.417     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.795     ; 3.035     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.186     ; 3.426     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.506     ; 3.746     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.560     ; 3.800     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.571     ; 3.811     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.806     ; 5.046     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.434     ; 4.674     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.989     ; 4.229     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.989     ; 4.229     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.979     ; 4.219     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.033     ; 4.273     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.023     ; 4.263     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.033     ; 4.273     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.514     ; 3.898     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.690     ; 1.690     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.057     ; 2.057     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.057     ; 2.057     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.057     ; 2.057     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.690     ; 1.690     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.066     ; 2.066     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.373     ; 2.373     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.425     ; 2.425     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.436     ; 2.436     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.622     ; 3.622     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.265     ; 3.265     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.838     ; 2.838     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.838     ; 2.838     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.828     ; 2.828     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.879     ; 2.879     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.869     ; 2.869     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.879     ; 2.879     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.558     ; 2.926     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 45.68 MHz  ; 45.68 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 138.22 MHz ; 138.22 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                    ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.669 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.628 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.388 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.403 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                 ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.711 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.937 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.470 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.559 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.571  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.319 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.587 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.837 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                     ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.669 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.780     ;
; 0.683 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.764     ;
; 0.792 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.656     ;
; 0.810 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.639     ;
; 0.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.623     ;
; 0.882 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.567     ;
; 0.896 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.551     ;
; 0.933 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.515     ;
; 0.967 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.472     ;
; 0.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.456     ;
; 1.001 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.447     ;
; 1.005 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.443     ;
; 1.010 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 10.423     ;
; 1.012 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.437     ;
; 1.026 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.421     ;
; 1.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 10.389     ;
; 1.061 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 10.373     ;
; 1.076 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 10.359     ;
; 1.090 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 10.348     ;
; 1.134 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.315     ;
; 1.135 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.313     ;
; 1.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.306     ;
; 1.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.299     ;
; 1.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 10.265     ;
; 1.214 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.234     ;
; 1.238 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 10.208     ;
; 1.257 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.191     ;
; 1.258 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 10.188     ;
; 1.262 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.185     ;
; 1.262 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 10.173     ;
; 1.273 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 10.160     ;
; 1.299 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 10.139     ;
; 1.304 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.144     ;
; 1.304 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.133     ;
; 1.324 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.124     ;
; 1.334 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 10.102     ;
; 1.344 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.104     ;
; 1.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 10.100     ;
; 1.379 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 10.056     ;
; 1.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.044     ;
; 1.423 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 10.036     ;
; 1.424 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 10.011     ;
; 1.430 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.018     ;
; 1.444 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 10.002     ;
; 1.466 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 9.982      ;
; 1.470 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 9.951      ;
; 1.475 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.972      ;
; 1.508 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.927      ;
; 1.520 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 9.914      ;
; 1.522 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 9.914      ;
; 1.536 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 9.898      ;
; 1.553 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.894      ;
; 1.560 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 9.877      ;
; 1.573 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[6]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 9.886      ;
; 1.591 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.844      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 9.849      ;
; 1.605 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.842      ;
; 1.628 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 9.806      ;
; 1.640 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 9.794      ;
; 1.645 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.790      ;
; 1.645 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.790      ;
; 1.650 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.785      ;
; 1.659 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 9.778      ;
; 1.663 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 9.785      ;
; 1.692 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 9.742      ;
; 1.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 9.736      ;
; 1.703 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 9.731      ;
; 1.709 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 9.727      ;
; 1.714 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 9.745      ;
; 1.718 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 9.716      ;
; 1.722 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 9.701      ;
; 1.727 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.720      ;
; 1.745 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 9.707      ;
; 1.762 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.685      ;
; 1.767 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.668      ;
; 1.791 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.644      ;
; 1.812 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.623      ;
; 1.817 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 9.628      ;
; 1.818 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 9.603      ;
; 1.822 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 9.635      ;
; 1.829 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.606      ;
; 1.853 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.594      ;
; 1.854 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.581      ;
; 1.862 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.573      ;
; 1.863 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.572      ;
; 1.866 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.581      ;
; 1.873 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.574      ;
; 1.927 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 9.509      ;
; 1.945 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.502      ;
; 1.948 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 9.477      ;
; 1.958 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 9.463      ;
; 1.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 9.494      ;
; 1.966 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 9.467      ;
; 1.970 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 9.465      ;
; 1.976 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 9.473      ;
; 1.976 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[6]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 9.484      ;
; 2.011 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 9.438      ;
; 2.014 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.433      ;
; 2.021 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 9.427      ;
; 2.023 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 9.423      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                              ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.628 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[5]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 8.947      ;
; 2.628 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 8.947      ;
; 2.653 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.941      ;
; 2.710 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.862      ;
; 2.837 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.757      ;
; 2.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.655      ;
; 2.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.655      ;
; 2.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.655      ;
; 2.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.655      ;
; 2.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.655      ;
; 2.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.655      ;
; 2.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.655      ;
; 2.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.655      ;
; 2.966 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 8.625      ;
; 2.971 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.602      ;
; 2.971 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.602      ;
; 2.971 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.602      ;
; 2.971 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.602      ;
; 2.971 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.602      ;
; 2.971 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.602      ;
; 2.971 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.602      ;
; 2.971 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.602      ;
; 3.062 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.512      ;
; 3.062 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[7]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.512      ;
; 3.062 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[2]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.512      ;
; 3.062 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[0]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.512      ;
; 3.062 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[1]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.512      ;
; 3.062 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[3]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.512      ;
; 3.085 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 8.511      ;
; 3.104 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.467      ;
; 3.106 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 8.490      ;
; 3.110 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.485      ;
; 3.139 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.455      ;
; 3.165 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 8.431      ;
; 3.191 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.404      ;
; 3.221 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.353      ;
; 3.221 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.353      ;
; 3.221 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.353      ;
; 3.221 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.353      ;
; 3.221 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.353      ;
; 3.221 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.353      ;
; 3.221 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.353      ;
; 3.221 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 8.353      ;
; 3.322 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.251      ;
; 3.326 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.245      ;
; 3.326 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.245      ;
; 3.326 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.245      ;
; 3.326 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.245      ;
; 3.326 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.245      ;
; 3.326 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.245      ;
; 3.326 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.245      ;
; 3.326 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.245      ;
; 3.329 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.265      ;
; 3.333 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 8.259      ;
; 3.337 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 8.259      ;
; 3.339 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 8.257      ;
; 3.341 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 8.251      ;
; 3.348 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.247      ;
; 3.363 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 8.229      ;
; 3.363 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 8.229      ;
; 3.363 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 8.229      ;
; 3.370 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 8.209      ;
; 3.383 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 8.216      ;
; 3.383 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.211      ;
; 3.385 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 8.213      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.187      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.187      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.187      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.187      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.187      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.187      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.187      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.187      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.210      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.210      ;
; 3.385 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.210      ;
; 3.386 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 8.210      ;
; 3.388 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.184      ;
; 3.388 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.184      ;
; 3.388 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.184      ;
; 3.388 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.184      ;
; 3.388 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.184      ;
; 3.388 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.184      ;
; 3.397 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.197      ;
; 3.397 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.197      ;
; 3.409 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 8.176      ;
; 3.460 ; ram_do_reg[6]              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 8.124      ;
; 3.467 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 8.125      ;
; 3.470 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.124      ;
; 3.491 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 8.101      ;
; 3.526 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.071      ;
; 3.549 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.045      ;
; 3.572 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.001      ;
; 3.584 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.989      ;
; 3.596 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 7.998      ;
; 3.635 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 7.957      ;
; 3.636 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 7.958      ;
; 3.659 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 7.937      ;
; 3.665 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 7.907      ;
; 3.665 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 7.907      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                   ; To Node                                                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.388 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                                   ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.041      ;
; 0.388 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                                   ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.041      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vbi_nmi_reg                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vbi_nmi_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig1_reg                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig1_reg                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig0_reg                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig0_reg                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig2_reg                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig2_reg                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg~_Duplicate_1                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg~_Duplicate_1                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|count_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|count_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[7]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|count_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|count_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[0]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[7]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[7]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.419 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.684      ;
; 0.479 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.744      ;
; 0.502 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.767      ;
; 0.641 ; sdram_ctrl:sdram_controller|r_wr_reg                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.907      ;
; 0.657 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.922      ;
; 0.670 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.935      ;
; 0.679 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.944      ;
; 0.683 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.949      ;
; 0.684 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.687 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.688 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.953      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.956      ;
; 0.694 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.694 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.959      ;
; 0.695 ; ram_bena_reg[1]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.696 ; ram_bena_reg[0]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.709 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.975      ;
; 0.729 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.995      ;
; 0.746 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.011      ;
; 0.755 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.020      ;
; 0.758 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.023      ;
; 0.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.172      ;
; 0.818 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.083      ;
; 0.847 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.112      ;
; 0.849 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.115      ;
; 0.870 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.135      ;
; 0.871 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.137      ;
; 0.873 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.246      ;
; 0.873 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.246      ;
; 0.873 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.242      ;
; 0.873 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.242      ;
; 0.875 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.244      ;
; 0.879 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.248      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.249      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.249      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.254      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.250      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.250      ;
; 0.882 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[13]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.255      ;
; 0.886 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[15]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.259      ;
; 0.887 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.152      ;
; 0.887 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.152      ;
; 0.888 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.154      ;
; 0.889 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.154      ;
; 0.889 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[12]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.262      ;
; 0.890 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.155      ;
; 0.891 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.264      ;
; 0.893 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.266      ;
; 0.893 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.266      ;
; 0.895 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.268      ;
; 0.895 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.268      ;
; 0.896 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.269      ;
; 0.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.268      ;
; 0.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.268      ;
; 0.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.268      ;
; 0.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.268      ;
; 0.908 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.173      ;
; 0.917 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.182      ;
; 0.940 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.205      ;
; 0.943 ; seq_reg[4]                                                                                                      ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.209      ;
; 0.944 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.209      ;
; 0.944 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.209      ;
; 0.948 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.213      ;
; 0.997 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[19]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.366      ;
; 0.998 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[26]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.367      ;
; 0.999 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.263      ;
; 0.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[25]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.368      ;
; 1.001 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.265      ;
; 1.003 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[24]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.372      ;
; 1.004 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[30]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.373      ;
; 1.005 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.271      ;
; 1.005 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.271      ;
; 1.005 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[21]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.374      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.010 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[29]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.379      ;
; 1.010 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[18]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.379      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.277      ;
; 1.012 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.278      ;
; 1.012 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[28]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 1.381      ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                    ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 5.889      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 5.889      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|clock_reg                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|clock_sync_reg                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_clock_reg                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 5.873      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 5.873      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 5.873      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 5.873      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[4]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 5.873      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|enabled_out_reg                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 5.873      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 5.881      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 5.883      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 5.883      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[7]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot0_reg[7]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[7]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot0_reg[3]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[3]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot0_reg[2]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[2]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 5.876      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 5.884      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot0_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 5.886      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 5.879      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 5.883      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.882      ;
; 5.711 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 5.889      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 5.877      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 5.870      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 5.870      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 5.873      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 5.869      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 5.865      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 5.865      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 5.874      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 5.866      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 5.866      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 5.867      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 5.867      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 5.866      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 5.884      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 5.866      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 5.866      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[15]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 5.868      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 5.873      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 5.876      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 5.870      ;
; 5.712 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 5.870      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 7.937 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.488      ;
; 7.937 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.488      ;
; 7.937 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.488      ;
; 7.937 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.488      ;
; 7.939 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.488      ;
; 7.939 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.486      ;
; 7.939 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.486      ;
; 7.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.357     ; 3.310      ;
; 7.947 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.365     ; 3.300      ;
; 7.947 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.365     ; 3.300      ;
; 7.947 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.365     ; 3.300      ;
; 7.950 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.365     ; 3.297      ;
; 7.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.366     ; 3.295      ;
; 7.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.370     ; 3.291      ;
; 7.952 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.372     ; 3.288      ;
; 7.964 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.475      ;
; 7.964 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.473      ;
; 7.964 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.473      ;
; 7.964 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.473      ;
; 7.964 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.474      ;
; 7.964 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.474      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.286      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.286      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.286      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.359     ; 3.284      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.359     ; 3.284      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.359     ; 3.284      ;
; 7.971 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.353     ; 3.288      ;
; 7.973 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.359     ; 3.280      ;
; 7.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.237     ; 3.404      ;
; 7.984 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.245     ; 3.394      ;
; 7.984 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.245     ; 3.394      ;
; 7.984 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.245     ; 3.394      ;
; 7.987 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.245     ; 3.391      ;
; 7.988 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.250     ; 3.385      ;
; 7.988 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.246     ; 3.389      ;
; 7.989 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.252     ; 3.382      ;
; 7.994 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.552      ;
; 7.994 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.552      ;
; 7.994 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.552      ;
; 7.994 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.552      ;
; 7.994 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.552      ;
; 7.995 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.552      ;
; 7.995 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.552      ;
; 7.995 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.552      ;
; 7.995 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.552      ;
; 7.995 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.552      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.550      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.550      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.550      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.550      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.550      ;
; 8.002 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 3.560      ;
; 8.005 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.380      ;
; 8.005 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.380      ;
; 8.005 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.380      ;
; 8.006 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 3.378      ;
; 8.006 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 3.378      ;
; 8.006 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 3.378      ;
; 8.008 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.233     ; 3.382      ;
; 8.010 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 3.374      ;
; 8.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.256      ;
; 8.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.256      ;
; 8.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.256      ;
; 8.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.256      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.105      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.105      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.105      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.105      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.096      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.096      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.096      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.096      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.096      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.095      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.095      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.108      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.110      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.096      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.108      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.096      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.095      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.095      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.095      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.095      ;
; 8.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.106      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.094      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.094      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.094      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.094      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.833      ;
; 2.471 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.831      ;
; 2.471 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.831      ;
; 2.471 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.831      ;
; 2.471 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.831      ;
; 2.471 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.831      ;
; 2.471 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.831      ;
; 2.471 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.831      ;
; 2.471 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.831      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.842      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.842      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.842      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.842      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.847      ;
; 2.472 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.843      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.833      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.833      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.845      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.834      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.834      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.845      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.834      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.833      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.833      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.833      ;
; 2.473 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.833      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.833      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.833      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.833      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.833      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.833      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.833      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.833      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.834      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.834      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.834      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.834      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.834      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.834      ;
; 2.474 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.834      ;
; 2.686 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.962      ;
; 2.686 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.962      ;
; 2.686 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.962      ;
; 2.686 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.962      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 3.233      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 3.233      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 3.233      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 3.233      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.234      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.234      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 3.233      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.234      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.131      ; 3.233      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.234      ;
; 2.888 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.234      ;
; 2.889 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.235      ;
; 2.889 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.235      ;
; 2.889 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.235      ;
; 2.889 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 3.235      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                 ;
+-------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.559 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[5]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.835      ;
; 4.562 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[6]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.837      ;
; 4.562 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[7]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.838      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[3]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 4.848      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[0][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[0][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.083      ; 4.849      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[7]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 4.845      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[6]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[2][1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][6]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 4.847      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[2][0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.571 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 4.846      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_enabled_reg                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][0]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count|value_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][1]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count|value_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[13][2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[12][2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[11][2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[10][2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[9][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[8][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[7][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[6][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[5][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[4][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[3][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[2][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[1][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 4.844      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count|value_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][3]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
; 4.572 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count|value_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.075      ; 4.842      ;
+-------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.575 ; 5.791        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.575 ; 5.791        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.575 ; 5.791        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.575 ; 5.791        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.575 ; 5.791        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.575 ; 5.791        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.575 ; 5.791        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.677 ; 5.832        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.678 ; 5.833        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.679 ; 5.834        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                          ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------+
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[13]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[14]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[15]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[16]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[17]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[18]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[19]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[20]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[21]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[22]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[23]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[0]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[10]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[11]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[1]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[2]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[3]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[4]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[5]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[6]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[7]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[8]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[9]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[0]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[10]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[11]                                                                                         ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[1]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[2]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[3]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[4]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[5]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[6]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[7]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[8]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[9]                                                                                          ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                            ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                            ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                            ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                            ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                            ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                            ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                            ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                            ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[2]                     ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[4]                     ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay|shift_reg[23] ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                   ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                   ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_speed_reg[1]                     ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                    ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                    ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                    ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                    ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                    ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                    ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                    ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg        ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|penh_reg[1]                          ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|penh_reg[3]                          ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|penh_reg[6]                          ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|penv_reg[1]                          ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|penv_reg[3]                          ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|penv_reg[6]                          ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[2]                        ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                    ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[12][0]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[12][1]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[12][2]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[12][3]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[12][4]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[12][5]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[12][6]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[12][7]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[23][0]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[23][1]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[23][2]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[23][3]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[23][4]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[23][5]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[23][6]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[23][7]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][1]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][2]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][4]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][5]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][6]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][0]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][1]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][2]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][3]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][4]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][5]  ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][6]  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.598 ; 17.598       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.643 ; 17.643       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.920  ; 99.920       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.079 ; 100.079      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.636 ; 2.743 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.651 ; 2.758 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.649 ; 2.756 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.645 ; 2.752 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.642 ; 2.749 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.638 ; 2.745 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.627 ; 2.734 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.049 ; 5.497 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.077 ; 4.521 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 3.478 ; 3.762 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 3.555 ; 3.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 3.345 ; 3.666 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 5.049 ; 5.497 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 4.887 ; 5.317 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.515 ; 3.738 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 3.592 ; 3.873 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 3.643 ; 3.968 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 3.454 ; 3.801 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 4.887 ; 5.317 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.114 ; 6.310 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.726 ; 5.860 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.544 ; 3.917 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.751 ; -1.859 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.767 ; -1.875 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.765 ; -1.873 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.761 ; -1.869 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.769 ; -1.877 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.757 ; -1.865 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.753 ; -1.861 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.399 ; -2.703 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.043 ; -3.440 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.526 ; -2.796 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.521 ; -2.796 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.399 ; -2.703 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.662 ; -2.940 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.505 ; -2.769 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.558 ; -2.769 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -2.578 ; -2.820 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.651 ; -2.942 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.505 ; -2.833 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.703 ; -2.962 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.067 ; -5.260 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -4.698 ; -4.827 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.605 ; -2.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                       ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317  ; 3.081  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326  ; 3.090  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336  ; 3.100  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346  ; 3.110  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325  ; 3.089  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.649  ; 4.201  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633  ; 4.185  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563  ; 2.365  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507  ; 3.264  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519  ; 3.276  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639  ; 3.382  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633  ; 3.376  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633  ; 3.376  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623  ; 3.366  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648  ; 4.200  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614  ; 3.357  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624  ; 3.367  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.400  ; 4.904  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.487  ; 3.903  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.400  ; 4.904  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345  ; 3.109  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.766  ; 7.812  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.496  ; 4.255  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.339  ; 3.903  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.458  ; 6.552  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.150  ; 3.404  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 12.525 ; 12.665 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 9.271  ; 9.054  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 12.525 ; 12.665 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.361  ; 9.018  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 11.106 ; 11.705 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 11.690 ; 11.883 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 11.690 ; 11.883 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 9.352  ; 8.974  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.685  ; 8.316  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 8.053  ; 7.706  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 7.605  ; 7.587  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 8.799  ; 8.447  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.623  ; 8.288  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 8.586  ; 8.199  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 8.397  ; 8.135  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.799  ; 8.447  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.486  ; 2.369  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.375  ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 9.104  ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.559 ; 2.327 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.578 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.588 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.859 ; 3.410 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.932 ; 3.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.917 ; 3.470 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.749 ; 2.510 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.760 ; 2.521 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.880 ; 2.627 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.940 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.864 ; 2.611 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.931 ; 3.484 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.855 ; 2.602 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.865 ; 2.612 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.722 ; 3.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.722 ; 3.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.599 ; 4.090 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.587 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.959 ; 7.018 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.718 ; 3.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.553 ; 3.129 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.697 ; 5.800 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.407 ; 2.654 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 4.554 ; 4.349 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 4.554 ; 4.349 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 7.404 ; 7.448 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 4.690 ; 4.417 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 7.610 ; 7.586 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 4.165 ; 3.831 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 6.779 ; 6.977 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 4.165 ; 3.831 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 4.617 ; 4.251 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 4.739 ; 4.214 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 6.591 ; 6.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 4.374 ; 4.112 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 4.374 ; 4.112 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 4.730 ; 4.514 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 4.629 ; 4.331 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 4.573 ; 4.265 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.766 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.697 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.431 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.919 ; 2.919 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.302 ; 3.302 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.302 ; 3.302 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.302 ; 3.302 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.919 ; 2.919 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.332 ; 3.332 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.646 ; 3.646 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.707 ; 3.707 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.718 ; 3.718 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.974 ; 4.974 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.601 ; 4.601 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.140 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.140 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.130 ; 4.130 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.173 ; 4.173 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.163 ; 4.163 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.173 ; 4.173 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.200 ; 3.824 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.877 ; 1.877 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.244 ; 2.244 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.244 ; 2.244 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.244 ; 2.244 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.877 ; 1.877 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.274 ; 2.274 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.576 ; 2.576 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.634 ; 2.634 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.644 ; 2.644 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.850 ; 3.850 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.493 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.050 ; 3.050 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.050 ; 3.050 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.040 ; 3.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.081 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.071 ; 3.071 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.081 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.322 ; 2.961 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.706     ; 2.777     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.057     ; 3.128     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.057     ; 3.128     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.057     ; 3.128     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.706     ; 2.777     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.068     ; 3.139     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.352     ; 3.423     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.411     ; 3.482     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.421     ; 3.492     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.578     ; 4.649     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.236     ; 4.307     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.820     ; 3.891     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.820     ; 3.891     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.810     ; 3.881     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.841     ; 3.912     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.831     ; 3.902     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.841     ; 3.912     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.513     ; 3.889     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.741     ; 1.877     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.077     ; 2.213     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.077     ; 2.213     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.077     ; 2.213     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.741     ; 1.877     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.089     ; 2.225     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.361     ; 2.497     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.417     ; 2.553     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.428     ; 2.564     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.539     ; 3.675     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.210     ; 3.346     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.811     ; 2.947     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.811     ; 2.947     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.801     ; 2.937     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.830     ; 2.966     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.820     ; 2.956     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.830     ; 2.966     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.663     ; 3.024     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                    ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 6.604 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.420 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.146 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.188 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                 ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.767 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.837 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.234 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.355 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.658  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.367 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.598 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.405 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                     ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 6.604 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 4.981      ;
; 6.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.931      ;
; 6.660 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 4.923      ;
; 6.668 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 4.917      ;
; 6.668 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 4.917      ;
; 6.691 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.891      ;
; 6.709 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.873      ;
; 6.717 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.867      ;
; 6.717 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.867      ;
; 6.718 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 4.867      ;
; 6.735 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 4.844      ;
; 6.747 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 4.833      ;
; 6.755 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.827      ;
; 6.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.827      ;
; 6.766 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.818      ;
; 6.767 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.817      ;
; 6.780 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 4.805      ;
; 6.784 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 4.794      ;
; 6.805 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.777      ;
; 6.822 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.754      ;
; 6.822 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.760      ;
; 6.829 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.755      ;
; 6.830 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.754      ;
; 6.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.754      ;
; 6.841 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 4.736      ;
; 6.867 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.715      ;
; 6.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.704      ;
; 6.891 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 4.686      ;
; 6.895 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 4.685      ;
; 6.897 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 4.681      ;
; 6.903 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 4.682      ;
; 6.933 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.649      ;
; 6.942 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.642      ;
; 6.944 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 4.634      ;
; 6.948 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 4.633      ;
; 6.952 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.632      ;
; 6.954 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 4.627      ;
; 6.957 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 4.624      ;
; 6.958 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.626      ;
; 6.961 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.623      ;
; 6.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 4.600      ;
; 6.988 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 4.592      ;
; 6.988 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 4.592      ;
; 6.989 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 4.591      ;
; 6.990 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.592      ;
; 6.991 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 4.588      ;
; 6.997 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.585      ;
; 6.997 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.585      ;
; 7.002 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[6]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 4.588      ;
; 7.022 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 4.557      ;
; 7.037 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 4.542      ;
; 7.040 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 4.538      ;
; 7.046 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 4.525      ;
; 7.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.535      ;
; 7.056 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 4.534      ;
; 7.056 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 4.523      ;
; 7.064 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.512      ;
; 7.065 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.519      ;
; 7.071 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.505      ;
; 7.074 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 4.504      ;
; 7.074 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 4.513      ;
; 7.074 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 4.516      ;
; 7.075 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 4.502      ;
; 7.078 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.498      ;
; 7.081 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.495      ;
; 7.099 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 4.473      ;
; 7.106 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.476      ;
; 7.109 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 4.470      ;
; 7.109 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 4.466      ;
; 7.109 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 4.473      ;
; 7.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 4.463      ;
; 7.113 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 4.467      ;
; 7.113 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.463      ;
; 7.125 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 4.456      ;
; 7.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 4.437      ;
; 7.138 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 4.443      ;
; 7.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 4.432      ;
; 7.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 4.442      ;
; 7.145 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.431      ;
; 7.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.431      ;
; 7.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 4.429      ;
; 7.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 4.432      ;
; 7.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 4.420      ;
; 7.159 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.417      ;
; 7.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 4.421      ;
; 7.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.401      ;
; 7.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 4.394      ;
; 7.193 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 4.387      ;
; 7.196 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.380      ;
; 7.202 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 4.376      ;
; 7.204 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 4.386      ;
; 7.207 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 4.376      ;
; 7.209 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 4.362      ;
; 7.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.117     ; 4.358      ;
; 7.215 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 4.359      ;
; 7.217 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 4.366      ;
; 7.218 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 4.363      ;
; 7.222 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 4.368      ;
; 7.223 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.353      ;
; 7.223 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 4.353      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                              ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 7.420 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[5]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.222      ;
; 7.420 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.222      ;
; 7.442 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 4.206      ;
; 7.466 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 4.170      ;
; 7.577 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.063      ;
; 7.577 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.063      ;
; 7.577 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.063      ;
; 7.577 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.063      ;
; 7.577 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.063      ;
; 7.577 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.063      ;
; 7.577 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.063      ;
; 7.577 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.063      ;
; 7.595 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 4.055      ;
; 7.610 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 4.027      ;
; 7.610 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 4.027      ;
; 7.610 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 4.027      ;
; 7.610 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 4.027      ;
; 7.610 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 4.027      ;
; 7.610 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 4.027      ;
; 7.610 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 4.027      ;
; 7.610 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 4.027      ;
; 7.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.009      ;
; 7.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[7]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.009      ;
; 7.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[2]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.009      ;
; 7.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[0]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.009      ;
; 7.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[1]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.009      ;
; 7.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[3]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 4.009      ;
; 7.633 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 4.016      ;
; 7.659 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.990      ;
; 7.680 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.958      ;
; 7.692 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.957      ;
; 7.707 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.944      ;
; 7.722 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.926      ;
; 7.724 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.925      ;
; 7.747 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.894      ;
; 7.747 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.894      ;
; 7.747 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.894      ;
; 7.747 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.894      ;
; 7.747 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.894      ;
; 7.747 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.894      ;
; 7.747 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.894      ;
; 7.747 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.894      ;
; 7.750 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.899      ;
; 7.768 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.880      ;
; 7.769 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.880      ;
; 7.771 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.878      ;
; 7.772 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.879      ;
; 7.776 ; ram_do_reg[6]              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 3.866      ;
; 7.777 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.874      ;
; 7.778 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.868      ;
; 7.788 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.857      ;
; 7.792 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.857      ;
; 7.794 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.852      ;
; 7.794 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.854      ;
; 7.812 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.826      ;
; 7.812 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.826      ;
; 7.812 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.826      ;
; 7.812 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.826      ;
; 7.812 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.826      ;
; 7.812 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.826      ;
; 7.812 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.826      ;
; 7.812 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.826      ;
; 7.822 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.829      ;
; 7.830 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.821      ;
; 7.835 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.811      ;
; 7.843 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 3.804      ;
; 7.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.775      ;
; 7.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.775      ;
; 7.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.775      ;
; 7.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.775      ;
; 7.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.775      ;
; 7.864 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.775      ;
; 7.867 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.779      ;
; 7.868 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.781      ;
; 7.868 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.781      ;
; 7.868 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.781      ;
; 7.871 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.775      ;
; 7.879 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.760      ;
; 7.879 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.760      ;
; 7.879 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.760      ;
; 7.879 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.760      ;
; 7.879 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.760      ;
; 7.879 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.760      ;
; 7.879 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.760      ;
; 7.879 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.760      ;
; 7.881 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.767      ;
; 7.884 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.764      ;
; 7.892 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.756      ;
; 7.892 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.756      ;
; 7.895 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 3.758      ;
; 7.895 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 3.758      ;
; 7.895 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 3.758      ;
; 7.901 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.750      ;
; 7.901 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.750      ;
; 7.913 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.736      ;
; 7.925 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 3.711      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.707      ;
; 7.935 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.716      ;
; 7.946 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.700      ;
; 7.951 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 3.685      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                   ; To Node                                                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.146 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                                   ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.470      ;
; 0.146 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                                   ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.470      ;
; 0.158 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                   ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.482      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|count_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|count_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[0]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[7]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[5]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CA2_output_reg                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CA2_output_reg                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[5]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[3]                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|cb2_edge_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|cb2_edge_reg                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CB2_output_reg                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CB2_output_reg                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[2]                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_overrun_reg                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_overrun_reg                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[4]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                  ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_reg                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                         ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.210 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.329      ;
; 0.210 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.329      ;
; 0.276 ; sdram_ctrl:sdram_controller|r_wr_reg                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.395      ;
; 0.286 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.404      ;
; 0.286 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.405      ;
; 0.287 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.406      ;
; 0.289 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.408      ;
; 0.292 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.297 ; ram_bena_reg[1]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.298 ; ram_bena_reg[0]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.417      ;
; 0.299 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.418      ;
; 0.300 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.309 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.428      ;
; 0.326 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.445      ;
; 0.331 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.517      ;
; 0.332 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.451      ;
; 0.333 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.452      ;
; 0.349 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.468      ;
; 0.359 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.478      ;
; 0.359 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.478      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.481      ;
; 0.367 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.487      ;
; 0.372 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.491      ;
; 0.373 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.492      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.559      ;
; 0.374 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.493      ;
; 0.374 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.493      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.375 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.561      ;
; 0.376 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.562      ;
; 0.377 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.496      ;
; 0.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.567      ;
; 0.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.567      ;
; 0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.568      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.569      ;
; 0.387 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.574      ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[13]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.575      ;
; 0.390 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.509      ;
; 0.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[15]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.580      ;
; 0.395 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.513      ;
; 0.396 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.514      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.583      ;
; 0.397 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[12]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.584      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.586      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.586      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.587      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.587      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.587      ;
; 0.406 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.525      ;
; 0.408 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.527      ;
; 0.415 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.534      ;
; 0.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[26]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.605      ;
; 0.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[19]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.605      ;
; 0.426 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[25]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.609      ;
; 0.428 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[24]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.611      ;
; 0.429 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[30]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.612      ;
; 0.430 ; seq_reg[4]                                                                                                      ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.550      ;
; 0.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[29]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.614      ;
; 0.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[21]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.614      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[28]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.618      ;
; 0.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[17]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.619      ;
; 0.437 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[18]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.620      ;
; 0.438 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[22]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.621      ;
; 0.439 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[20]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.622      ;
; 0.439 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[23]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.622      ;
; 0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[31]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.623      ;
; 0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[27]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 0.623      ;
; 0.441 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.561      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                     ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 8.767 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.874      ;
; 8.767 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.874      ;
; 8.767 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.881      ;
; 8.767 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.874      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.879      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.877      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 2.888      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.876      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.872      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.872      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 2.887      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.880      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.874      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.874      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 2.887      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.873      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.873      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[15]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.875      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.883      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.873      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.873      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.883      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.876      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[25]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.879      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.875      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.879      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.880      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 2.888      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.872      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 2.870      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 2.870      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[4]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.879      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[5]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.879      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.876      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.877      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 2.870      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.879      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[9]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[8]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.879      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.872      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[11]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[10]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.873      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.873      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.883      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.872      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.874      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.874      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.880      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.873      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 2.870      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.879      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.884      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[5]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.884      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|clock_reg                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.884      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|clock_sync_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.884      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_clock_reg                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.884      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|sio_in_reg                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[2]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[3]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|enabled_out_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.878      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[3]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 2.882      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 2.885      ;
; 8.768 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 2.886      ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 9.837  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.712      ;
; 9.839  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.654      ;
; 9.840  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.141     ; 1.706      ;
; 9.840  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.141     ; 1.706      ;
; 9.840  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.141     ; 1.706      ;
; 9.841  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 1.704      ;
; 9.842  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 1.648      ;
; 9.842  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 1.648      ;
; 9.842  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 1.648      ;
; 9.843  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 1.646      ;
; 9.843  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 1.702      ;
; 9.844  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 1.697      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 1.644      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.775      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.775      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.775      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 1.694      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.775      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.775      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 1.639      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.773      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.773      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.773      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.775      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.775      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.773      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.775      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.773      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.775      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.775      ;
; 9.847  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 1.636      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.720      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.720      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.720      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.720      ;
; 9.850  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.140     ; 1.697      ;
; 9.850  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.140     ; 1.697      ;
; 9.850  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.140     ; 1.697      ;
; 9.851  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.718      ;
; 9.851  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.718      ;
; 9.852  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 1.639      ;
; 9.852  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 1.639      ;
; 9.852  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 1.639      ;
; 9.852  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.697      ;
; 9.852  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.697      ;
; 9.852  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.697      ;
; 9.852  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.719      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.639      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.639      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.639      ;
; 9.855  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.698      ;
; 9.855  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.140     ; 1.692      ;
; 9.855  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.775      ;
; 9.857  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 1.634      ;
; 9.857  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.640      ;
; 9.864  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.712      ;
; 9.864  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.711      ;
; 9.864  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.711      ;
; 9.865  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.713      ;
; 9.865  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 1.712      ;
; 9.865  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 1.712      ;
; 9.968  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.603      ;
; 9.968  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.603      ;
; 9.969  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.602      ;
; 9.969  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.602      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.562      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.557      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.557      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.557      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.557      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.552      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.552      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.559      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.559      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.553      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.552      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.552      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.552      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.552      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.558      ;
; 10.077 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.551      ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.417      ;
; 1.234 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.421      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.417      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.417      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.417      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.417      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.419      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.419      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.414      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.413      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.412      ;
; 1.235 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.418      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.413      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.413      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.413      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.413      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.413      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.413      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.413      ;
; 1.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.413      ;
; 1.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.068      ; 1.468      ;
; 1.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.068      ; 1.468      ;
; 1.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.068      ; 1.468      ;
; 1.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.068      ; 1.468      ;
; 1.423 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.602      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.582      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.580      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.581      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.065      ; 1.598      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.065      ; 1.598      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.065      ; 1.598      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.066      ; 1.599      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.066      ; 1.599      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.065      ; 1.598      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.066      ; 1.599      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.065      ; 1.598      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.066      ; 1.599      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.066      ; 1.599      ;
; 1.430 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.581      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                 ;
+-------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.355 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[6]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.484      ;
; 2.355 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[7]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.046      ; 2.485      ;
; 2.355 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[5]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.482      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_enabled_reg                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][0]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count|value_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][1]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count|value_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][2]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count|value_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][3]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count|value_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.038      ; 2.482      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.038      ; 2.482      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.038      ; 2.482      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.038      ; 2.482      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.038      ; 2.482      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.038      ; 2.482      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[3]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 2.487      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.042      ; 2.486      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][2]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.042      ; 2.486      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.489      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.489      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.489      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.489      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.489      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][5]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[4][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[3][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[2][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[1][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.039      ; 2.483      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][5]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][2]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.042      ; 2.486      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp2_delay|shift_reg[0][3]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.042      ; 2.486      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][6]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[0]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 2.481      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[4]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][4]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[5]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][5]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][5]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][5]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][5]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][5]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[2][7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[2][1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[1][1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[0][1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.041      ; 2.485      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[7]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.040      ; 2.484      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.489      ;
; 2.360 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][7]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.489      ;
+-------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.660 ; 5.876        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.661 ; 5.877        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.662 ; 5.817        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.662 ; 5.817        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                       ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a11~porta_address_reg0                                                                                  ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a14~porta_address_reg0                                                                                  ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a20~porta_address_reg0                                                                                  ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a23~porta_address_reg0                                                                                  ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a2~porta_address_reg0                                                                                   ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a3~porta_address_reg0                                                                                   ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a7~porta_address_reg0                                                                                   ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                             ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                             ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                        ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                              ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_r|altsyncram:Ram0_rtl_0|altsyncram_kt71:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_r|altsyncram:Ram0_rtl_0|altsyncram_kt71:auto_generated|ram_block1a7~porta_address_reg0 ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a10~porta_address_reg0                                                                                  ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a17~porta_address_reg0                                                                                  ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a1~porta_address_reg0                                                                                   ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a21~porta_address_reg0                                                                                  ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a4~porta_address_reg0                                                                                   ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a5~porta_address_reg0                                                                                   ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a6~porta_address_reg0                                                                                   ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a8~porta_address_reg0                                                                                   ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                      ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                            ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                        ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                        ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                         ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_l|altsyncram:Ram0_rtl_0|altsyncram_kt71:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_l|altsyncram:Ram0_rtl_0|altsyncram_kt71:auto_generated|ram_block1a7~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processInt                                                                 ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processIrq                                                                 ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processNmi                                                                 ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[13]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[14]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[15]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[16]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[17]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[18]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[19]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[20]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[21]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[22]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[23]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[0]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[10]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[11]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[12]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[13]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[14]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[15]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[16]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[17]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[18]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[19]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[1]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[20]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[21]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[22]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[23]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[2]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[3]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[4]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[5]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[6]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[7]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[8]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p2[9]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[0]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[10]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[11]                                                                                                                                                      ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[1]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[2]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[3]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[4]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[5]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[6]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[7]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[8]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_lpf_p2[9]                                                                                                                                                       ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                         ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                         ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                         ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                         ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                          ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                         ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                                                         ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                         ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                         ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][0]                                                               ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][1]                                                               ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][2]                                                               ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][3]                                                               ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][4]                                                               ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][5]                                                               ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][6]                                                               ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][7]                                                               ;
; 17.407 ; 17.623       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][0]                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.612 ; 17.612       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.629 ; 17.629       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.549 ; 100.549      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.561 ; 100.561      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.491 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.489 ; 2.047 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.485 ; 2.043 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.483 ; 2.041 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.471 ; 2.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 2.768 ; 3.212 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 2.297 ; 2.766 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 1.946 ; 2.464 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 1.981 ; 2.494 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 1.867 ; 2.400 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 2.768 ; 3.212 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 2.692 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 2.015 ; 2.484 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 2.012 ; 2.500 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 2.052 ; 2.560 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 1.957 ; 2.459 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 2.692 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.317 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 3.116 ; 3.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 1.983 ; 2.484 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.014 ; -1.572 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.371 ; -1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.755 ; -2.214 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.447 ; -1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.447 ; -1.941 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.371 ; -1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.544 ; -2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.456 ; -1.953 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.512 ; -1.978 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.481 ; -1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -1.534 ; -2.022 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -1.456 ; -1.953 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.568 ; -2.058 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.764 ; -3.576 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.570 ; -3.305 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.486 ; -1.989 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.596 ; 1.445 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.604 ; 1.453 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.613 ; 1.462 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.615 ; 1.464 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.625 ; 1.474 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.609 ; 1.458 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.594 ; 2.300 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.633 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.622 ; 2.344 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.163 ; 1.075 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.685 ; 1.535 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.695 ; 1.545 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.764 ; 1.618 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.632 ; 2.354 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.756 ; 1.610 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.766 ; 1.620 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.234 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.687 ; 1.679 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.234 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.629 ; 1.478 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.932 ; 4.574 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 2.001 ; 2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.843 ; 1.956 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.329 ; 3.877 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.489 ; 1.442 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 6.097 ; 6.598 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 4.198 ; 4.260 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 6.097 ; 6.598 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 4.191 ; 4.420 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.705 ; 6.095 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.863 ; 6.349 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.863 ; 6.349 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 4.219 ; 4.278 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 3.956 ; 3.973 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 3.699 ; 3.735 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 4.408 ; 3.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 4.013 ; 4.092 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 3.897 ; 3.914 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 3.834 ; 3.915 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 3.829 ; 3.850 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 4.013 ; 4.092 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.088 ; 1.054 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.368 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.315 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.266 ; 1.262 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.266 ; 1.262 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.792 ; 1.732 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.500 ; 4.136 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.582 ; 1.713 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.420 ; 1.527 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 2.917 ; 3.462 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.080 ; 1.036 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.970 ; 2.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.993 ; 2.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 3.700 ; 4.247 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.970 ; 2.088 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 3.758 ; 4.403 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.754 ; 1.778 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 3.492 ; 3.973 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.754 ; 1.778 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.939 ; 1.971 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.943 ; 2.097 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 3.844 ; 3.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.858 ; 1.868 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.858 ; 1.868 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.061 ; 2.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.953 ; 2.003 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.949 ; 1.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.995 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.941 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.130 ; 2.103 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.311 ; 2.284 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.311 ; 2.284 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.311 ; 2.284 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.130 ; 2.103 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.322 ; 2.295 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.467 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.505 ; 2.478 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.515 ; 2.488 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.097 ; 3.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.916 ; 2.889 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.708 ; 2.681 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.708 ; 2.681 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.698 ; 2.671 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.708 ; 2.681 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.698 ; 2.671 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.708 ; 2.681 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.914 ; 2.538 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.831 ; 0.831 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.004 ; 1.004 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.004 ; 1.004 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.004 ; 1.004 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 0.831 ; 0.831 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.015 ; 1.015 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.155 ; 1.155 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.191 ; 1.191 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.201 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.760 ; 1.760 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.586 ; 1.586 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.387 ; 1.387 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.387 ; 1.387 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.377 ; 1.377 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.386 ; 1.386 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.376 ; 1.376 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.386 ; 1.386 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.395 ; 2.034 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.191     ; 2.191     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.386     ; 2.386     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.386     ; 2.386     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.386     ; 2.386     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.191     ; 2.191     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.393     ; 2.393     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.560     ; 2.560     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.590     ; 2.590     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.601     ; 2.601     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.276     ; 3.276     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.081     ; 3.081     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.843     ; 2.843     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.843     ; 2.843     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.833     ; 2.833     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.849     ; 2.849     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.839     ; 2.839     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.849     ; 2.849     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.656     ; 3.032     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.890     ; 1.007     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.077     ; 1.194     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.077     ; 1.194     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.077     ; 1.194     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 0.890     ; 1.007     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.084     ; 1.201     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.244     ; 1.361     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.273     ; 1.390     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.284     ; 1.401     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.932     ; 2.049     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.745     ; 1.862     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.516     ; 1.633     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.516     ; 1.633     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.506     ; 1.623     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.521     ; 1.638     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.511     ; 1.628     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.521     ; 1.638     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.148     ; 2.509     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                       ;
+--------------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+
; Clock                                                                          ; Setup ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+
; Worst-case Slack                                                               ; 0.110 ; 0.146 ; 5.186    ; 1.234   ; 5.571               ;
;  FPGA_CLK                                                                      ; N/A   ; N/A   ; N/A      ; N/A     ; 99.405              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.110 ; 0.188 ; 7.594    ; 1.234   ; 5.571               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.076 ; 0.146 ; 5.186    ; 2.355   ; 17.319              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A   ; N/A   ; N/A      ; N/A     ; 17.584              ;
; Design-wide TNS                                                                ; 0.0   ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  FPGA_CLK                                                                      ; N/A   ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A   ; N/A   ; N/A      ; N/A     ; 0.000               ;
+--------------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.023 ; 3.130 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026 ; 3.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.724 ; 6.016 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.664 ; 4.962 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 3.956 ; 4.184 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.063 ; 4.288 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 3.830 ; 4.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 5.724 ; 6.016 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 5.528 ; 5.811 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.014 ; 4.171 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.109 ; 4.306 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.163 ; 4.409 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 3.959 ; 4.212 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 5.528 ; 5.811 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.933 ; 7.280 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.523 ; 6.772 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.056 ; 4.334 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.014 ; -1.572 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.371 ; -1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.755 ; -2.214 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.447 ; -1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.447 ; -1.941 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.371 ; -1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.544 ; -2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.456 ; -1.953 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.512 ; -1.978 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.481 ; -1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -1.534 ; -2.022 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -1.456 ; -1.953 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.568 ; -2.058 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.764 ; -3.576 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.570 ; -3.305 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.486 ; -1.989 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                       ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317  ; 3.081  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326  ; 3.090  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336  ; 3.100  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346  ; 3.110  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325  ; 3.089  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.649  ; 4.201  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633  ; 4.185  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563  ; 2.365  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507  ; 3.264  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519  ; 3.276  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639  ; 3.382  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633  ; 3.376  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633  ; 3.376  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623  ; 3.366  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648  ; 4.200  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614  ; 3.357  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624  ; 3.367  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.408  ; 4.904  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.487  ; 3.903  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.408  ; 4.904  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345  ; 3.109  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.766  ; 7.812  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.496  ; 4.255  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.339  ; 3.903  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.458  ; 6.552  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.150  ; 3.404  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 12.599 ; 12.840 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 9.303  ; 9.189  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 12.599 ; 12.840 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.458  ; 9.191  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 11.315 ; 11.817 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 11.734 ; 11.969 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 11.734 ; 11.969 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 9.417  ; 9.151  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.800  ; 8.523  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 8.116  ; 7.838  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 7.628  ; 7.587  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 8.882  ; 8.702  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.633  ; 8.367  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 8.607  ; 8.357  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 8.446  ; 8.243  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.882  ; 8.702  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.486  ; 2.369  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.375  ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 9.104  ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.266 ; 1.262 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.266 ; 1.262 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.792 ; 1.732 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.500 ; 4.136 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.582 ; 1.713 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.420 ; 1.527 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 2.917 ; 3.462 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.080 ; 1.036 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.970 ; 2.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.993 ; 2.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 3.700 ; 4.247 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.970 ; 2.088 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 3.758 ; 4.403 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.754 ; 1.778 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 3.492 ; 3.973 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.754 ; 1.778 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.939 ; 1.971 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.943 ; 2.097 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 3.844 ; 3.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.858 ; 1.868 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.858 ; 1.868 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.061 ; 2.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.953 ; 2.003 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.949 ; 1.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.995 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.941 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1806     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 10741    ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7323     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3797663  ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1806     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 10741    ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7323     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3797663  ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2305     ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2305     ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 29    ; 29   ;
; Unconstrained Input Port Paths  ; 61    ; 61   ;
; Unconstrained Output Ports      ; 55    ; 55   ;
; Unconstrained Output Port Paths ; 157   ; 157  ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Aug 21 07:28:59 2014
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 234.00 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 0.110
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.110         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.076         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.415
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.415         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.454         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 5.186
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.186         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.594         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 2.763
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.763         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.020         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.571
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.571         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.320         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.584         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.862         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.669
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.669         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.628         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.388
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.388         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.403         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 5.711
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.711         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.937         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 2.470
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.470         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.559         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.571
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.571         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.319         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.587         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.837         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 6.604
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.604         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.420         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.146
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.146         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.188         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 8.767
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     8.767         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.837         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 1.234
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.234         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.355         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.658
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.658         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.367         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.598         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.405         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 497 megabytes
    Info: Processing ended: Thu Aug 21 07:29:22 2014
    Info: Elapsed time: 00:00:23
    Info: Total CPU time (on all processors): 00:00:26


