TimeQuest Timing Analyzer report for atari800core
Mon Nov  3 22:23:37 2014
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 15. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 16. Slow 1200mV 85C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Setup: 'altera_reserved_tck'
 18. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 19. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'altera_reserved_tck'
 21. Slow 1200mV 85C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 23. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 24. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 25. Slow 1200mV 85C Model Recovery: 'altera_reserved_tck'
 26. Slow 1200mV 85C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 27. Slow 1200mV 85C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 28. Slow 1200mV 85C Model Removal: 'altera_reserved_tck'
 29. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 30. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 34. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck'
 37. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 38. Setup Times
 39. Hold Times
 40. Clock to Output Times
 41. Minimum Clock to Output Times
 42. Output Enable Times
 43. Minimum Output Enable Times
 44. Output Disable Times
 45. Minimum Output Disable Times
 46. Slow 1200mV 85C Model Metastability Report
 47. Slow 1200mV 0C Model Fmax Summary
 48. Slow 1200mV 0C Model Setup Summary
 49. Slow 1200mV 0C Model Hold Summary
 50. Slow 1200mV 0C Model Recovery Summary
 51. Slow 1200mV 0C Model Removal Summary
 52. Slow 1200mV 0C Model Minimum Pulse Width Summary
 53. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 54. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 55. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 56. Slow 1200mV 0C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 57. Slow 1200mV 0C Model Setup: 'altera_reserved_tck'
 58. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 59. Slow 1200mV 0C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 60. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 61. Slow 1200mV 0C Model Hold: 'altera_reserved_tck'
 62. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 63. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 64. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 65. Slow 1200mV 0C Model Recovery: 'altera_reserved_tck'
 66. Slow 1200mV 0C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 68. Slow 1200mV 0C Model Removal: 'altera_reserved_tck'
 69. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 70. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 71. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 72. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 74. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 75. Slow 1200mV 0C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 76. Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'
 77. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 78. Setup Times
 79. Hold Times
 80. Clock to Output Times
 81. Minimum Clock to Output Times
 82. Output Enable Times
 83. Minimum Output Enable Times
 84. Output Disable Times
 85. Minimum Output Disable Times
 86. Slow 1200mV 0C Model Metastability Report
 87. Fast 1200mV 0C Model Setup Summary
 88. Fast 1200mV 0C Model Hold Summary
 89. Fast 1200mV 0C Model Recovery Summary
 90. Fast 1200mV 0C Model Removal Summary
 91. Fast 1200mV 0C Model Minimum Pulse Width Summary
 92. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 93. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 94. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 95. Fast 1200mV 0C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 96. Fast 1200mV 0C Model Setup: 'altera_reserved_tck'
 97. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 98. Fast 1200mV 0C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 99. Fast 1200mV 0C Model Hold: 'altera_reserved_tck'
100. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
101. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
102. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
103. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
104. Fast 1200mV 0C Model Recovery: 'altera_reserved_tck'
105. Fast 1200mV 0C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
106. Fast 1200mV 0C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Removal: 'altera_reserved_tck'
108. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
109. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
110. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
111. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
112. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
113. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
114. Fast 1200mV 0C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
115. Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'
116. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
117. Setup Times
118. Hold Times
119. Clock to Output Times
120. Minimum Clock to Output Times
121. Output Enable Times
122. Minimum Output Enable Times
123. Output Disable Times
124. Minimum Output Disable Times
125. Fast 1200mV 0C Model Metastability Report
126. Multicorner Timing Analysis Summary
127. Setup Times
128. Hold Times
129. Clock to Output Times
130. Minimum Clock to Output Times
131. Board Trace Model Assignments
132. Input Transition Times
133. Signal Integrity Metrics (Slow 1200mv 0c Model)
134. Signal Integrity Metrics (Slow 1200mv 85c Model)
135. Signal Integrity Metrics (Fast 1200mv 0c Model)
136. Setup Transfers
137. Hold Transfers
138. Recovery Transfers
139. Removal Transfers
140. Report TCCS
141. Report RSKM
142. Unconstrained Paths
143. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
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(including device programming or simulation files), and any 
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Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
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Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone IV E                                                      ;
; Device Name        ; EP4CE15E22C7                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.22        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  22.2%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Mon Nov  3 22:22:56 2014 ;
+------------------+--------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-------------------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; Clock Name                                                                    ; Type      ; Period  ; Frequency  ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                       ; Source                                                                          ; Targets                                                                           ;
+-------------------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz  ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz  ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz  ; 7.341 ; 13.214  ; 50.00      ; 1         ; 3           ; 225.0 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Generated ; 8.810   ; 113.51 MHz ; 0.000 ; 4.405   ; 50.00      ; 1         ; 4           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz  ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; altera_reserved_tck                                                           ; Base      ; 100.000 ; 10.0 MHz   ; 0.000 ; 50.000  ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                              ;                                                                                 ; { altera_reserved_tck }                                                           ;
; FPGA_CLK                                                                      ; Base      ; 200.000 ; 5.0 MHz    ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                              ;                                                                                 ; { FPGA_CLK }                                                                      ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; Generated ; 66.666  ; 15.0 MHz   ; 0.000 ; 33.333  ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                     ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                          ; { mcc_pll3|altpll_component|auto_generated|pll1|clk[0] }                          ;
+-------------------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 48.37 MHz  ; 48.37 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 68.82 MHz  ; 68.82 MHz       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;      ;
; 120.71 MHz ; 120.71 MHz      ; altera_reserved_tck                                                           ;      ;
; 135.19 MHz ; 135.19 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 237.98 MHz ; 237.98 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                    ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -8.386 ; -917.212      ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.177 ; -0.533        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.608  ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 26.068 ; 0.000         ;
; altera_reserved_tck                                                           ; 45.858 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                    ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.339 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.412 ; 0.000         ;
; altera_reserved_tck                                                           ; 0.413 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.413 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.440 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                 ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.736  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.119  ; 0.000         ;
; altera_reserved_tck                                                           ; 48.258 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 63.187 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                 ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.633 ; 0.000         ;
; altera_reserved_tck                                                           ; 1.012 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.422 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.292 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                      ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.130  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.595  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.336 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.594 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 33.035 ; 0.000         ;
; altera_reserved_tck                                                           ; 49.485 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.796 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                                                 ; Launch Clock                                         ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -8.386 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.371     ; 6.161      ;
; -8.378 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.371     ; 6.153      ;
; -8.195 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 6.381      ;
; -8.150 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.957     ; 6.339      ;
; -8.100 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.933     ; 6.313      ;
; -8.084 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.919     ; 6.311      ;
; -8.062 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 6.248      ;
; -8.020 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.996     ; 6.170      ;
; -7.974 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.963     ; 6.157      ;
; -7.957 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.936     ; 6.167      ;
; -7.940 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.933     ; 6.153      ;
; -7.936 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.963     ; 6.119      ;
; -7.919 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.936     ; 6.129      ;
; -7.915 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.922     ; 6.139      ;
; -7.877 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.922     ; 6.101      ;
; -7.874 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.381     ; 5.639      ;
; -7.854 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.957     ; 6.043      ;
; -7.831 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.933     ; 6.044      ;
; -7.795 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.365     ; 5.576      ;
; -7.789 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.999     ; 5.936      ;
; -7.789 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.365     ; 5.570      ;
; -7.787 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.963     ; 5.970      ;
; -7.763 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.919     ; 5.990      ;
; -7.755 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.932     ; 5.969      ;
; -7.751 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.999     ; 5.898      ;
; -7.740 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.933     ; 5.953      ;
; -7.740 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.963     ; 5.923      ;
; -7.738 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.359     ; 5.525      ;
; -7.721 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.359     ; 5.508      ;
; -7.720 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.359     ; 5.507      ;
; -7.717 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.382     ; 5.481      ;
; -7.714 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.366     ; 5.494      ;
; -7.714 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.359     ; 5.501      ;
; -7.700 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.932     ; 5.914      ;
; -7.679 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.382     ; 5.443      ;
; -7.671 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.352     ; 5.465      ;
; -7.649 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.364     ; 5.431      ;
; -7.643 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.364     ; 5.425      ;
; -7.611 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.000     ; 5.757      ;
; -7.611 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.000     ; 5.757      ;
; -7.608 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.359     ; 5.395      ;
; -7.577 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.356     ; 5.367      ;
; -7.573 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.000     ; 5.719      ;
; -7.573 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.000     ; 5.719      ;
; -7.554 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.935     ; 5.765      ;
; -7.545 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.938     ; 5.753      ;
; -7.540 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.936     ; 5.750      ;
; -7.539 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.356     ; 5.329      ;
; -7.536 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.957     ; 5.725      ;
; -7.525 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[2]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.302      ;
; -7.522 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.359     ; 5.309      ;
; -7.517 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[2]   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.295      ;
; -7.516 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[24] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.353     ; 5.309      ;
; -7.513 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 5.699      ;
; -7.507 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.938     ; 5.715      ;
; -7.506 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.364     ; 5.288      ;
; -7.506 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.365     ; 5.287      ;
; -7.495 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.957     ; 5.684      ;
; -7.493 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.936     ; 5.703      ;
; -7.492 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.933     ; 5.705      ;
; -7.489 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.364     ; 5.271      ;
; -7.481 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 5.667      ;
; -7.475 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 5.661      ;
; -7.469 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[1]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.372     ; 5.243      ;
; -7.466 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 5.242      ;
; -7.443 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 5.629      ;
; -7.431 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[1]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.372     ; 5.205      ;
; -7.430 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.360     ; 5.216      ;
; -7.428 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 5.204      ;
; -7.424 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.360     ; 5.210      ;
; -7.420 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.936     ; 5.630      ;
; -7.420 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.365     ; 5.201      ;
; -7.419 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.353     ; 5.212      ;
; -7.417 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.932     ; 5.631      ;
; -7.417 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.932     ; 5.631      ;
; -7.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 5.599      ;
; -7.410 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.968     ; 5.588      ;
; -7.410 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.359     ; 5.197      ;
; -7.385 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.991     ; 5.540      ;
; -7.383 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.372     ; 5.157      ;
; -7.382 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.957     ; 5.571      ;
; -7.379 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.957     ; 5.568      ;
; -7.378 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.367     ; 5.157      ;
; -7.376 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.364     ; 5.158      ;
; -7.375 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 5.561      ;
; -7.373 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.922     ; 5.597      ;
; -7.358 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.364     ; 5.140      ;
; -7.354 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.936     ; 5.564      ;
; -7.345 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.935     ; 5.556      ;
; -7.345 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.372     ; 5.119      ;
; -7.342 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.935     ; 5.553      ;
; -7.324 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.359     ; 5.111      ;
; -7.313 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.936     ; 5.523      ;
; -7.308 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.367     ; 5.087      ;
; -7.307 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.935     ; 5.518      ;
; -7.305 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.922     ; 5.529      ;
; -7.304 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.935     ; 5.515      ;
; -7.303 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.367     ; 5.082      ;
; -7.292 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.366     ; 5.072      ;
; -7.290 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.364     ; 5.072      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.602     ;
; -0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 11.622     ;
; -0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.585     ;
; -0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.605     ;
; -0.111 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 11.561     ;
; -0.103 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.544     ;
; -0.100 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 11.562     ;
; -0.097 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.551     ;
; -0.085 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 11.507     ;
; -0.076 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.529     ;
; -0.069 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 11.491     ;
; -0.051 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 11.501     ;
; -0.036 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.473     ;
; -0.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.473     ;
; -0.017 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.466     ;
; -0.010 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.452     ;
; -0.003 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 11.464     ;
; 0.009  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.416     ;
; 0.011  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.430     ;
; 0.020  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.433     ;
; 0.032  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.393     ;
; 0.032  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.405     ;
; 0.036  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.401     ;
; 0.068  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.374     ;
; 0.069  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.372     ;
; 0.078  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.371     ;
; 0.084  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.365     ;
; 0.097  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.351     ;
; 0.107  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 11.345     ;
; 0.125  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.323     ;
; 0.127  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.310     ;
; 0.140  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.308     ;
; 0.184  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 11.252     ;
; 0.192  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.233     ;
; 0.194  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 11.246     ;
; 0.200  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 11.234     ;
; 0.212  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 11.224     ;
; 0.212  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 11.222     ;
; 0.227  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.222     ;
; 0.227  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 11.209     ;
; 0.241  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.184     ;
; 0.251  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 11.210     ;
; 0.252  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 11.209     ;
; 0.254  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.194     ;
; 0.261  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 11.189     ;
; 0.262  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.207     ; 11.161     ;
; 0.269  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.172     ;
; 0.269  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.207     ; 11.154     ;
; 0.276  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.161     ;
; 0.283  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 11.139     ;
; 0.314  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.142     ;
; 0.321  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 11.129     ;
; 0.322  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 11.139     ;
; 0.324  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.118     ;
; 0.333  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 11.089     ;
; 0.338  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.111     ;
; 0.339  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.110     ;
; 0.341  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 11.095     ;
; 0.345  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.096     ;
; 0.359  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.078     ;
; 0.363  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 11.061     ;
; 0.380  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.623     ; 10.627     ;
; 0.382  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.055     ;
; 0.384  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.041     ;
; 0.393  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.044     ;
; 0.395  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 11.029     ;
; 0.401  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.043     ;
; 0.402  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.040     ;
; 0.404  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.033     ;
; 0.405  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 11.032     ;
; 0.409  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.040     ;
; 0.418  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.031     ;
; 0.427  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 10.998     ;
; 0.440  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.013     ;
; 0.441  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.000     ;
; 0.451  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 10.996     ;
; 0.461  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.994     ;
; 0.467  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.635     ; 10.528     ;
; 0.489  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 10.952     ;
; 0.490  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 10.961     ;
; 0.499  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 10.938     ;
; 0.518  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 10.918     ;
; 0.522  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 10.926     ;
; 0.524  ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 10.928     ;
; 0.527  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 10.926     ;
; 0.528  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 10.912     ;
; 0.536  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.920     ;
; 0.546  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 10.893     ;
; 0.546  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 10.890     ;
; 0.548  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 10.895     ;
; 0.549  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.913     ;
; 0.552  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 10.882     ;
; 0.554  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 10.881     ;
; 0.557  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 10.896     ;
; 0.561  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 10.875     ;
; 0.564  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 10.858     ;
; 0.567  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.889     ;
; 0.577  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 10.862     ;
; 0.578  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.884     ;
; 0.586  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 10.836     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                         ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.608 ; svideo_yout_dly2[6]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 4.002      ;
; 4.615 ; svideo_yout_dly2[5]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.995      ;
; 4.632 ; svideo_yout_dly2[6]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.080     ; 3.981      ;
; 4.635 ; svideo_yout_dly2[5]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.080     ; 3.978      ;
; 4.654 ; svideo_yout_dly2[6]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.956      ;
; 4.661 ; svideo_yout_dly2[5]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.949      ;
; 4.704 ; svideo_yout_dly2[6]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.908      ;
; 4.708 ; svideo_yout_dly2[5]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.904      ;
; 4.735 ; svideo_yout_dly2[6]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.877      ;
; 4.741 ; svideo_yout_dly2[5]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.871      ;
; 4.781 ; svideo_yout_dly2[6]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.831      ;
; 4.788 ; svideo_yout_dly2[5]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.824      ;
; 4.913 ; svideo_yout_dly2[4]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.697      ;
; 4.914 ; svideo_yout_dly2[7]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.696      ;
; 4.923 ; svideo_yout_dly2[7]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.080     ; 3.690      ;
; 4.937 ; svideo_yout_dly2[4]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.080     ; 3.676      ;
; 4.953 ; svideo_yout_dly2[6]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.659      ;
; 4.959 ; svideo_yout_dly2[4]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.651      ;
; 4.960 ; svideo_yout_dly2[5]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.652      ;
; 4.963 ; svideo_yout_dly2[7]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.647      ;
; 4.996 ; svideo_yout_dly2[7]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.616      ;
; 5.009 ; svideo_yout_dly2[4]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.603      ;
; 5.029 ; svideo_yout_dly2[7]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.583      ;
; 5.040 ; svideo_yout_dly2[4]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.572      ;
; 5.086 ; svideo_yout_dly2[4]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.526      ;
; 5.115 ; svideo_yout_dly2[7]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.497      ;
; 5.138 ; svideo_yout_dly2[6]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.082     ; 3.473      ;
; 5.143 ; svideo_yout_dly2[3]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.467      ;
; 5.145 ; svideo_yout_dly2[5]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.082     ; 3.466      ;
; 5.159 ; svideo_yout_dly2[2]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.451      ;
; 5.167 ; svideo_yout_dly2[3]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.080     ; 3.446      ;
; 5.168 ; svideo_yout_dly2[2]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.080     ; 3.445      ;
; 5.189 ; svideo_yout_dly2[3]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.421      ;
; 5.208 ; svideo_yout_dly2[2]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.402      ;
; 5.229 ; svideo_yout_dly2[1]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.381      ;
; 5.239 ; svideo_yout_dly2[3]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.373      ;
; 5.241 ; svideo_yout_dly2[2]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.371      ;
; 5.253 ; svideo_yout_dly2[1]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.080     ; 3.360      ;
; 5.258 ; svideo_yout_dly2[4]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.354      ;
; 5.270 ; svideo_yout_dly2[3]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.342      ;
; 5.274 ; svideo_yout_dly2[2]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.338      ;
; 5.275 ; svideo_yout_dly2[1]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.335      ;
; 5.284 ; svideo_yout_dly2[7]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.328      ;
; 5.316 ; svideo_yout_dly2[3]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.296      ;
; 5.325 ; svideo_yout_dly2[1]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.287      ;
; 5.356 ; svideo_yout_dly2[1]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.256      ;
; 5.360 ; svideo_yout_dly2[2]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.252      ;
; 5.402 ; svideo_yout_dly2[1]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.210      ;
; 5.443 ; svideo_yout_dly2[4]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.082     ; 3.168      ;
; 5.488 ; svideo_yout_dly2[3]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.124      ;
; 5.495 ; svideo_yout_dly2[7]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.082     ; 3.116      ;
; 5.516 ; svideo_yout_dly2[0]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.094      ;
; 5.525 ; svideo_yout_dly2[0]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.080     ; 3.088      ;
; 5.529 ; svideo_yout_dly2[2]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.083      ;
; 5.565 ; svideo_yout_dly2[0]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.083     ; 3.045      ;
; 5.574 ; svideo_yout_dly2[1]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.038      ;
; 5.598 ; svideo_yout_dly2[0]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 3.014      ;
; 5.631 ; svideo_yout_dly2[0]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 2.981      ;
; 5.673 ; svideo_yout_dly2[3]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.082     ; 2.938      ;
; 5.717 ; svideo_yout_dly2[0]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 2.895      ;
; 5.740 ; svideo_yout_dly2[2]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.082     ; 2.871      ;
; 5.759 ; svideo_yout_dly2[1]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.082     ; 2.852      ;
; 5.886 ; svideo_yout_dly2[0]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.081     ; 2.726      ;
; 6.034 ; svideo:svideo|luma[2]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.592      ;
; 6.095 ; svideo:svideo|chroma[0] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.532      ;
; 6.097 ; svideo_yout_dly2[0]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.082     ; 2.514      ;
; 6.106 ; svideo:svideo|luma[1]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.520      ;
; 6.112 ; cvbs1_out[3]            ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.079     ; 2.502      ;
; 6.113 ; svideo:svideo|luma[0]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.513      ;
; 6.123 ; svideo:svideo|luma[1]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.503      ;
; 6.132 ; svideo:svideo|luma[0]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.494      ;
; 6.144 ; svideo:svideo|chroma[1] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.483      ;
; 6.144 ; cvbs1_out[4]            ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.079     ; 2.470      ;
; 6.163 ; svideo:svideo|chroma[1] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.464      ;
; 6.166 ; svideo:svideo|luma[2]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.460      ;
; 6.179 ; svideo:svideo|luma[4]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.447      ;
; 6.185 ; svideo:svideo|luma[2]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.441      ;
; 6.198 ; svideo:svideo|chroma[2] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.429      ;
; 6.213 ; svideo:svideo|chroma[3] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.414      ;
; 6.220 ; cvbs1_out[9]            ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.078     ; 2.395      ;
; 6.227 ; svideo:svideo|chroma[0] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.400      ;
; 6.232 ; svideo:svideo|chroma[3] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.395      ;
; 6.238 ; svideo:svideo|luma[1]   ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.388      ;
; 6.243 ; svideo:svideo|chroma[0] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.384      ;
; 6.245 ; svideo:svideo|luma[0]   ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.381      ;
; 6.255 ; svideo:svideo|luma[1]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.371      ;
; 6.264 ; svideo:svideo|luma[0]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.362      ;
; 6.265 ; svideo:svideo|luma_2[1] ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.069     ; 2.474      ;
; 6.269 ; svideo:svideo|luma[3]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.357      ;
; 6.276 ; svideo:svideo|chroma[1] ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.351      ;
; 6.283 ; svideo:svideo|luma[3]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.343      ;
; 6.284 ; svideo:svideo|luma_2[1] ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.069     ; 2.455      ;
; 6.295 ; svideo:svideo|chroma[1] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.332      ;
; 6.298 ; svideo:svideo|luma[2]   ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.328      ;
; 6.311 ; svideo:svideo|luma[4]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.315      ;
; 6.317 ; svideo:svideo|luma[2]   ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.309      ;
; 6.326 ; cvbs1_out[2]            ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.079     ; 2.288      ;
; 6.330 ; svideo:svideo|luma[4]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.182     ; 2.296      ;
; 6.330 ; svideo:svideo|chroma[2] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.297      ;
; 6.338 ; svideo:svideo|chroma[2] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.181     ; 2.289      ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                     ; To Node                                                         ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 26.068 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 7.166      ;
; 26.068 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 7.166      ;
; 26.091 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 7.143      ;
; 26.091 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 7.143      ;
; 26.142 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 7.094      ;
; 26.142 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 7.094      ;
; 26.149 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 7.086      ;
; 26.149 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 7.086      ;
; 26.165 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 7.070      ;
; 26.165 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 7.070      ;
; 26.306 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.930      ;
; 26.306 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.930      ;
; 26.307 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 6.927      ;
; 26.307 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 6.927      ;
; 26.400 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.835      ;
; 26.400 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.835      ;
; 26.431 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 6.803      ;
; 26.431 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 6.803      ;
; 26.473 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 6.761      ;
; 26.473 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 6.761      ;
; 26.524 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.711      ;
; 26.524 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.711      ;
; 26.566 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.669      ;
; 26.566 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.669      ;
; 26.627 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 6.607      ;
; 26.627 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.087     ; 6.607      ;
; 26.649 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.587      ;
; 26.649 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.587      ;
; 26.694 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.535      ;
; 26.710 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.519      ;
; 26.717 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.518      ;
; 26.717 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.518      ;
; 26.770 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.459      ;
; 26.793 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.436      ;
; 26.860 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.376      ;
; 26.860 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.376      ;
; 26.877 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.359      ;
; 26.877 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.359      ;
; 26.929 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.300      ;
; 26.945 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.284      ;
; 26.953 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.276      ;
; 26.971 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[0]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.101     ; 6.249      ;
; 27.009 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.220      ;
; 27.044 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[9]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.101     ; 6.176      ;
; 27.044 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.101     ; 6.176      ;
; 27.048 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.181      ;
; 27.064 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.165      ;
; 27.074 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.155      ;
; 27.077 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.152      ;
; 27.080 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.149      ;
; 27.080 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.149      ;
; 27.081 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.148      ;
; 27.083 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.146      ;
; 27.090 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.139      ;
; 27.100 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.129      ;
; 27.101 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.134      ;
; 27.101 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.134      ;
; 27.103 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.126      ;
; 27.104 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.125      ;
; 27.106 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.123      ;
; 27.109 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.120      ;
; 27.118 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[0]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.101     ; 6.102      ;
; 27.124 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.111      ;
; 27.124 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.111      ;
; 27.125 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.104      ;
; 27.131 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.098      ;
; 27.133 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.096      ;
; 27.175 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.054      ;
; 27.175 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.061      ;
; 27.175 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.061      ;
; 27.188 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.041      ;
; 27.239 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 5.997      ;
; 27.239 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 5.997      ;
; 27.253 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 5.983      ;
; 27.253 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 5.983      ;
; 27.262 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.967      ;
; 27.271 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.958      ;
; 27.273 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.956      ;
; 27.276 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[12]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.953      ;
; 27.278 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.951      ;
; 27.279 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.950      ;
; 27.282 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.947      ;
; 27.287 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.942      ;
; 27.289 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.940      ;
; 27.292 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[12]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.937      ;
; 27.294 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.935      ;
; 27.295 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.934      ;
; 27.303 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.926      ;
; 27.315 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.914      ;
; 27.316 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.913      ;
; 27.319 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.910      ;
; 27.319 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.910      ;
; 27.320 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.909      ;
; 27.322 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.907      ;
; 27.329 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 5.900      ;
; 27.337 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.100     ; 5.884      ;
; 27.337 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.100     ; 5.884      ;
; 27.337 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.100     ; 5.884      ;
; 27.337 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.100     ; 5.884      ;
; 27.337 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.100     ; 5.884      ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                             ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 45.858 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.146      ; 4.286      ;
; 45.870 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.147      ; 4.275      ;
; 46.068 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.146      ; 4.076      ;
; 46.434 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.195      ; 3.759      ;
; 46.452 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.727      ;
; 46.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.520      ;
; 46.740 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.146      ; 3.404      ;
; 46.749 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.430      ;
; 46.755 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.424      ;
; 46.770 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.409      ;
; 46.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.372      ;
; 46.809 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.370      ;
; 46.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.202      ;
; 46.981 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.180      ; 3.197      ;
; 47.176 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.003      ;
; 47.205 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.146      ; 2.939      ;
; 47.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.180      ; 2.926      ;
; 47.282 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 2.897      ;
; 47.315 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.180      ; 2.863      ;
; 47.341 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.194      ; 2.851      ;
; 47.479 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 2.700      ;
; 47.558 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.180      ; 2.620      ;
; 48.013 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.180      ; 2.165      ;
; 48.025 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.180      ; 2.153      ;
; 94.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 5.348      ;
; 94.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 5.348      ;
; 94.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 5.348      ;
; 94.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 5.348      ;
; 94.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 5.348      ;
; 94.965 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.355     ; 4.678      ;
; 94.980 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.355     ; 4.663      ;
; 95.045 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.355     ; 4.598      ;
; 95.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.830      ;
; 95.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.830      ;
; 95.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.830      ;
; 95.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.830      ;
; 95.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.830      ;
; 95.103 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.355     ; 4.540      ;
; 95.116 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.813      ;
; 95.116 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.813      ;
; 95.116 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.813      ;
; 95.116 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.813      ;
; 95.116 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.813      ;
; 95.126 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.355     ; 4.517      ;
; 95.135 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.355     ; 4.508      ;
; 95.168 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.355     ; 4.475      ;
; 95.253 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.678      ;
; 95.253 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.678      ;
; 95.253 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.678      ;
; 95.253 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.678      ;
; 95.253 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.678      ;
; 95.290 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.356      ;
; 95.301 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.345      ;
; 95.313 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.615      ;
; 95.313 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.615      ;
; 95.313 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.615      ;
; 95.313 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.615      ;
; 95.313 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.615      ;
; 95.338 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.308      ;
; 95.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.118     ; 4.463      ;
; 95.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.118     ; 4.463      ;
; 95.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.118     ; 4.463      ;
; 95.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.118     ; 4.463      ;
; 95.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.118     ; 4.463      ;
; 95.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.118     ; 4.463      ;
; 95.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.118     ; 4.463      ;
; 95.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.118     ; 4.463      ;
; 95.442 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.204      ;
; 95.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.482      ;
; 95.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.482      ;
; 95.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.482      ;
; 95.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.482      ;
; 95.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.482      ;
; 95.453 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.355     ; 4.190      ;
; 95.458 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.188      ;
; 95.463 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.183      ;
; 95.468 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.178      ;
; 95.474 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.172      ;
; 95.549 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.380      ;
; 95.549 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.380      ;
; 95.549 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.380      ;
; 95.549 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.380      ;
; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.327      ;
; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.327      ;
; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.327      ;
; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.327      ;
; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.327      ;
; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.327      ;
; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.327      ;
; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.327      ;
; 95.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.322      ;
; 95.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.322      ;
; 95.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.322      ;
; 95.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.322      ;
; 95.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 4.322      ;
; 95.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 4.272      ;
; 95.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.260      ;
; 95.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.260      ;
; 95.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.260      ;
; 95.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 4.260      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.339 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 0.996      ;
; 0.342 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[3]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 0.998      ;
; 0.342 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.000      ;
; 0.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.000      ;
; 0.345 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.003      ;
; 0.345 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.002      ;
; 0.345 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.003      ;
; 0.346 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.002      ;
; 0.347 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.005      ;
; 0.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[2]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.005      ;
; 0.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.437      ; 1.008      ;
; 0.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.007      ;
; 0.351 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.008      ;
; 0.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[5]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.009      ;
; 0.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.010      ;
; 0.355 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.012      ;
; 0.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.016      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.019      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.020      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.021      ;
; 0.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.025      ;
; 0.368 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.025      ;
; 0.368 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.024      ;
; 0.370 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[4]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.026      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.032      ;
; 0.375 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.032      ;
; 0.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[6]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.033      ;
; 0.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep2_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.437      ; 1.036      ;
; 0.378 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.027      ;
; 0.378 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.026      ;
; 0.381 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.034      ;
; 0.381 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.430      ; 1.033      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.036      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.430      ; 1.035      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.437      ; 1.043      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep2_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.437      ; 1.045      ;
; 0.387 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|cntr_4pf:cntr1|counter_reg_bit[0]    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~portb_address_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.036      ;
; 0.387 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|cntr_4pf:cntr1|counter_reg_bit[0]    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_address_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.035      ;
; 0.390 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.039      ;
; 0.390 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.038      ;
; 0.395 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.395 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[1]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.051      ;
; 0.396 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 0.669      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 0.669      ;
; 0.407 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.065      ;
; 0.411 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[2]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[2]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[1]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[1]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[7]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[7]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[4]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[4]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[5]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[5]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[6]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[6]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_clock_reg                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_clock_reg                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[1]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[1]                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_reset_reg                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_reset_reg                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_overrun_reg                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_overrun_reg                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[0]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[0]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_clock_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_clock_reg                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[0]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[0]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[2]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[2]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[3]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[3]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.412 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.674      ;
; 0.487 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dq_oe             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.743      ;
; 0.526 ; seq_reg[0]                                                                                                      ; seq_reg[1]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.782      ;
; 0.596 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.853      ;
; 0.598 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.855      ;
; 0.599 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.856      ;
; 0.627 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.883      ;
; 0.631 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.888      ;
; 0.631 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 1.007      ;
; 0.632 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 1.008      ;
; 0.634 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.890      ;
; 0.641 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.897      ;
; 0.644 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.900      ;
; 0.644 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.900      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.649 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.905      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.654 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.910      ;
; 0.662 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.918      ;
; 0.666 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.922      ;
; 0.666 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.922      ;
; 0.673 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.928      ;
; 0.679 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.935      ;
; 0.684 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.939      ;
; 0.696 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.771 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.027      ;
; 0.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.140      ;
; 0.783 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.147      ;
; 0.800 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.056      ;
; 0.813 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.069      ;
; 0.845 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]  ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 1.210      ;
; 0.846 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.103      ;
; 0.853 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 1.229      ;
; 0.854 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.109      ;
; 0.863 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.227      ;
; 0.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.229      ;
; 0.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 1.230      ;
; 0.866 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.230      ;
; 0.873 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 1.238      ;
; 0.895 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]  ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 1.260      ;
; 0.914 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.170      ;
; 0.931 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 1.307      ;
; 0.962 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.218      ;
; 0.962 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.218      ;
; 0.964 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.964 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.967 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.223      ;
; 0.971 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 1.347      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.229      ;
; 0.975 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.231      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.233      ;
; 0.978 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.234      ;
; 0.980 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.236      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.238      ;
; 0.983 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.347      ;
; 0.991 ; sdram_request_reg                                                                                               ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.247      ;
; 1.011 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.266      ;
; 1.015 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.271      ;
; 1.024 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.280      ;
; 1.048 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.304      ;
; 1.061 ; sdram_ctrl:sdram_controller|r_rddata[4]                                                                         ; ram_do_reg[20]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.230      ; 1.477      ;
; 1.065 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.429      ;
; 1.068 ; sdram_ctrl:sdram_controller|r_rddata[1]                                                                         ; ram_do_reg[17]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 1.472      ;
; 1.070 ; sdram_ctrl:sdram_controller|r_rddata[2]                                                                         ; ram_do_reg[18]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 1.474      ;
; 1.074 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.329      ;
; 1.083 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.339      ;
; 1.083 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.339      ;
; 1.085 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.341      ;
; 1.088 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.344      ;
; 1.088 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.344      ;
; 1.090 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.346      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.355      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.357      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.358      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.358      ;
; 1.103 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.359      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.360      ;
; 1.106 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.362      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.363      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.363      ;
; 1.114 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.369      ;
; 1.116 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]  ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.480      ;
; 1.124 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.488      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                             ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.674      ;
; 0.419 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.674      ;
; 0.419 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.674      ;
; 0.431 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.687      ;
; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.692      ;
; 0.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.694      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.695      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.696      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.696      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.441 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.441 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.697      ;
; 0.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.698      ;
; 0.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.697      ;
; 0.447 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.702      ;
; 0.447 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.702      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.703      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.703      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.703      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.703      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.704      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.704      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.704      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.704      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.704      ;
; 0.453 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.709      ;
; 0.453 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.709      ;
; 0.454 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.709      ;
; 0.454 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.709      ;
; 0.454 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.709      ;
; 0.454 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.710      ;
; 0.455 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.710      ;
; 0.455 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.710      ;
; 0.459 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.714      ;
; 0.461 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.716      ;
; 0.462 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.717      ;
; 0.462 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.717      ;
; 0.462 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.718      ;
; 0.463 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.718      ;
; 0.463 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.718      ;
; 0.463 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.718      ;
; 0.463 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.718      ;
; 0.464 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.719      ;
; 0.464 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.719      ;
; 0.466 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.721      ;
; 0.469 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.724      ;
; 0.470 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.051      ;
; 0.472 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.356      ; 1.050      ;
; 0.478 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.733      ;
; 0.478 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.733      ;
; 0.479 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.356      ; 1.057      ;
; 0.481 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.356      ; 1.059      ;
; 0.485 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.066      ;
; 0.508 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.089      ;
; 0.512 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.093      ;
; 0.518 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.099      ;
; 0.520 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.356      ; 1.098      ;
; 0.523 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.356      ; 1.101      ;
; 0.541 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.122      ;
; 0.542 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.123      ;
; 0.564 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.819      ;
; 0.564 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.819      ;
; 0.564 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.819      ;
; 0.565 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.820      ;
; 0.567 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.822      ;
; 0.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 0.821      ;
; 0.567 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.148      ;
; 0.572 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.827      ;
; 0.585 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.841      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                           ; To Node                                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[1]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[6]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[6]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[7]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[7]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[4]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[4]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[5]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[5]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[0]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[2]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[2]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[4]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[4]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[7]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[7]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|val                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|val                                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid                    ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp_previous                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm_previous                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; cntr_reset[1]                                                       ; cntr_reset[1]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; cntr_reset[2]                                                       ; cntr_reset[2]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; cntr_reset[5]                                                       ; cntr_reset[5]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; cntr_reset[6]                                                       ; cntr_reset[6]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; reset_usbdrv                                                        ; reset_usbdrv                                                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start           ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte7         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte7         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte8         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte8         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte9         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte9         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte10        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte10        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte11        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte11        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait40                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait40                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait6                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait6                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte5         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte5         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte6         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte6         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[1]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_wait1     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_wait1     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack_end            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack_end            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                            ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                 ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.440 ; svideo:svideo|luma_acc[9] ; svideo_yout_dly1[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.696      ;
; 0.441 ; svideo:svideo|luma_acc[4] ; svideo_yout_dly1[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.697      ;
; 0.442 ; svideo_yout_dly1[3]       ; svideo_yout_dly2[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.698      ;
; 0.442 ; svideo_yout_dly1[5]       ; svideo_yout_dly2[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.698      ;
; 0.501 ; svideo:svideo|luma[6]     ; svideo:svideo|luma_1[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 0.865      ;
; 0.562 ; svideo:svideo|luma[5]     ; svideo:svideo|luma_1[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.925      ;
; 0.565 ; svideo:svideo|luma[7]     ; svideo:svideo|luma_1[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.928      ;
; 0.565 ; svideo:svideo|luma[9]     ; svideo:svideo|luma_1[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.928      ;
; 0.597 ; svideo:svideo|luma_2[9]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.853      ;
; 0.597 ; svideo:svideo|luma_acc[3] ; svideo_yout_dly1[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 0.852      ;
; 0.601 ; svideo_yout_dly1[6]       ; svideo_yout_dly2[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.857      ;
; 0.606 ; svideo:svideo|luma_acc[6] ; svideo_yout_dly1[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 0.861      ;
; 0.606 ; svideo:svideo|luma_acc[8] ; svideo_yout_dly1[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 0.861      ;
; 0.608 ; svideo:svideo|luma_1[3]   ; svideo:svideo|luma_2[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.864      ;
; 0.613 ; svideo_yout_dly1[0]       ; svideo_yout_dly2[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.869      ;
; 0.629 ; svideo:svideo|luma_1[2]   ; svideo:svideo|luma_2[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.885      ;
; 0.630 ; svideo:svideo|luma_1[5]   ; svideo:svideo|luma_2[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.886      ;
; 0.632 ; svideo:svideo|luma_1[0]   ; svideo:svideo|luma_2[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.888      ;
; 0.646 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.902      ;
; 0.647 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.903      ;
; 0.649 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.905      ;
; 0.652 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.908      ;
; 0.663 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.919      ;
; 0.715 ; svideo:svideo|luma[6]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.079      ;
; 0.726 ; svideo:svideo|luma[7]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.089      ;
; 0.726 ; svideo:svideo|luma[9]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.089      ;
; 0.727 ; svideo:svideo|chroma[8]   ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.091      ;
; 0.763 ; svideo:svideo|luma[5]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.126      ;
; 0.775 ; svideo:svideo|luma_1[9]   ; svideo:svideo|luma_2[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.031      ;
; 0.777 ; svideo:svideo|luma_1[8]   ; svideo:svideo|luma_2[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.033      ;
; 0.783 ; svideo:svideo|luma[3]     ; svideo:svideo|luma_1[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.161      ; 1.148      ;
; 0.794 ; svideo:svideo|luma[0]     ; luma_saturated[0]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.158      ;
; 0.800 ; svideo:svideo|luma[0]     ; svideo:svideo|luma_1[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.164      ;
; 0.802 ; luma_saturated[3]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.057      ;
; 0.804 ; svideo:svideo|luma[2]     ; svideo:svideo|luma_1[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.161      ; 1.169      ;
; 0.809 ; svideo:svideo|luma[1]     ; svideo:svideo|luma_1[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.173      ;
; 0.810 ; luma_saturated[2]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.065      ;
; 0.811 ; luma_saturated[6]         ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.066      ;
; 0.812 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.068      ;
; 0.813 ; svideo:svideo|luma_1[6]   ; svideo:svideo|luma_2[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.069      ;
; 0.816 ; svideo:svideo|luma_1[7]   ; svideo:svideo|luma_2[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.072      ;
; 0.824 ; svideo:svideo|luma_acc[7] ; svideo_yout_dly1[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.080      ;
; 0.829 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.085      ;
; 0.837 ; svideo:svideo|luma_1[1]   ; svideo:svideo|luma_2[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.093      ;
; 0.847 ; luma_saturated[4]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.102      ;
; 0.850 ; luma_saturated[5]         ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.105      ;
; 0.851 ; luma_saturated[9]         ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.106      ;
; 0.854 ; luma_saturated[7]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.109      ;
; 0.856 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.112      ;
; 0.856 ; svideo_yout_dly1[1]       ; svideo_yout_dly2[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.112      ;
; 0.857 ; svideo:svideo|luma_2[3]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.113      ;
; 0.859 ; svideo_yout_dly1[4]       ; svideo_yout_dly2[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.115      ;
; 0.862 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.118      ;
; 0.910 ; svideo:svideo|chroma[4]   ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.274      ;
; 0.917 ; svideo:svideo|chroma[6]   ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.281      ;
; 0.945 ; svideo:svideo|chroma[2]   ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.309      ;
; 0.956 ; svideo:svideo|chroma[7]   ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.320      ;
; 0.959 ; svideo:svideo|chroma[8]   ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.323      ;
; 0.963 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.219      ;
; 0.964 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.220      ;
; 0.964 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.220      ;
; 0.967 ; svideo:svideo|luma[4]     ; svideo:svideo|luma_1[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.161      ; 1.332      ;
; 0.976 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.232      ;
; 0.979 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.235      ;
; 0.981 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.237      ;
; 0.984 ; svideo:svideo|luma[8]     ; svideo:svideo|luma_1[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.161      ; 1.349      ;
; 0.989 ; svideo:svideo|luma[3]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.161      ; 1.354      ;
; 0.992 ; svideo:svideo|chroma[5]   ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.356      ;
; 0.999 ; svideo:svideo|chroma[3]   ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.363      ;
; 0.999 ; svideo:svideo|luma_acc[2] ; svideo_yout_dly1[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.255      ;
; 1.004 ; svideo:svideo|luma[4]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.161      ; 1.369      ;
; 1.005 ; svideo_yout_dly1[7]       ; svideo_yout_dly2[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.261      ;
; 1.008 ; svideo_yout_dly1[2]       ; svideo_yout_dly2[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.264      ;
; 1.011 ; svideo:svideo|luma[8]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.161      ; 1.376      ;
; 1.011 ; svideo:svideo|luma_1[4]   ; svideo:svideo|luma_2[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.267      ;
; 1.013 ; svideo:svideo|luma[2]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.161      ; 1.378      ;
; 1.026 ; svideo:svideo|luma_acc[5] ; svideo_yout_dly1[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.282      ;
; 1.026 ; svideo:svideo|luma_2[1]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.282      ;
; 1.029 ; svideo:svideo|luma[6]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.393      ;
; 1.041 ; svideo:svideo|luma[0]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.405      ;
; 1.050 ; luma_saturated[8]         ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.305      ;
; 1.051 ; svideo:svideo|luma[1]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.160      ; 1.415      ;
; 1.055 ; svideo:svideo|luma[7]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.418      ;
; 1.060 ; svideo:svideo|luma[7]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.423      ;
; 1.084 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.340      ;
; 1.085 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.341      ;
; 1.085 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.341      ;
; 1.089 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.345      ;
; 1.090 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.346      ;
; 1.092 ; svideo:svideo|luma[5]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.455      ;
; 1.097 ; svideo:svideo|luma[5]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.460      ;
; 1.102 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.358      ;
; 1.107 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.363      ;
; 1.118 ; luma_saturated[3]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.373      ;
; 1.122 ; luma_saturated[1]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.377      ;
; 1.139 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.395      ;
; 1.139 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.395      ;
; 1.140 ; luma_saturated[2]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.395      ;
; 1.140 ; luma_saturated[6]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.395      ;
; 1.144 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.400      ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                               ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                              ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.736 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 6.846      ;
; 4.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 6.797      ;
; 4.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 6.797      ;
; 4.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 6.797      ;
; 4.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 6.797      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 6.810      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 6.810      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 6.810      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 6.433      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 6.434      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 6.433      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 6.433      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 6.433      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 6.423      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 6.423      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.436      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 6.433      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[21] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 6.435      ;
; 5.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 6.438      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 6.419      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 6.419      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 6.419      ;
; 5.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 6.435      ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                 ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 8.119 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.262     ; 3.242      ;
; 8.189 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.258      ;
; 8.189 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.258      ;
; 8.189 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.257      ;
; 8.189 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.257      ;
; 8.192 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.253      ;
; 8.192 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.252      ;
; 8.192 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.252      ;
; 8.206 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.094      ;
; 8.208 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.329     ; 3.085      ;
; 8.211 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.323     ; 3.088      ;
; 8.211 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.323     ; 3.088      ;
; 8.211 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.323     ; 3.088      ;
; 8.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.246      ;
; 8.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.085      ;
; 8.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.085      ;
; 8.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.085      ;
; 8.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 3.246      ;
; 8.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 3.246      ;
; 8.214 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.207      ;
; 8.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.241      ;
; 8.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.241      ;
; 8.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.241      ;
; 8.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.241      ;
; 8.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.241      ;
; 8.216 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.198      ;
; 8.219 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 3.201      ;
; 8.219 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 3.201      ;
; 8.219 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 3.201      ;
; 8.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.198      ;
; 8.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.198      ;
; 8.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.198      ;
; 8.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.313     ; 3.081      ;
; 8.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.314     ; 3.080      ;
; 8.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.072      ;
; 8.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.313     ; 3.079      ;
; 8.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.082      ;
; 8.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.082      ;
; 8.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.082      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.185      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.193      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.194      ;
; 8.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.195      ;
; 8.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.195      ;
; 8.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.195      ;
; 8.238 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.192      ;
; 8.343 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.235      ;
; 8.343 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.235      ;
; 8.343 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.235      ;
; 8.343 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.235      ;
; 8.343 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.235      ;
; 8.438 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.009      ;
; 8.461 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 2.997      ;
; 8.461 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 2.997      ;
; 8.462 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 2.996      ;
; 8.462 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 2.996      ;
; 8.462 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 2.996      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.868      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.868      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.868      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.868      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.868      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.868      ;
; 8.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 2.857      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.721 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 2.861      ;
; 8.722 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 2.861      ;
; 8.722 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 2.861      ;
; 8.722 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 2.861      ;
; 8.722 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 2.861      ;
; 8.722 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 2.861      ;
; 8.722 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 2.861      ;
; 8.722 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 2.861      ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 48.258 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.180      ; 1.920      ;
; 96.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 3.128      ;
; 96.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 3.128      ;
; 96.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 3.128      ;
; 96.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 3.128      ;
; 97.094 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 2.801      ;
; 97.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 2.787      ;
; 97.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 2.787      ;
; 97.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 2.787      ;
; 97.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.103     ; 2.787      ;
; 97.393 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 2.536      ;
; 97.393 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 2.536      ;
; 97.393 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 2.536      ;
; 97.393 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 2.536      ;
; 97.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 2.362      ;
; 97.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 2.362      ;
; 97.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 2.362      ;
; 97.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 2.362      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.767 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.164      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.784 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.082     ; 2.132      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 2.019      ;
; 98.000 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.929      ;
; 98.000 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.929      ;
; 98.000 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.929      ;
; 98.000 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.929      ;
; 98.000 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.929      ;
; 98.000 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.929      ;
; 98.000 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.929      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.019 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.910      ;
; 98.025 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.904      ;
; 98.025 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.904      ;
; 98.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.889      ;
; 98.040 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.889      ;
; 98.041 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.886      ;
; 98.041 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.886      ;
; 98.041 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.886      ;
; 98.044 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.083     ; 1.871      ;
; 98.044 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.083     ; 1.871      ;
; 98.044 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.083     ; 1.871      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.874      ;
; 98.522 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.407      ;
; 98.522 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.407      ;
; 98.522 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.407      ;
; 98.522 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.407      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                             ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.088     ; 3.379      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.088     ; 3.379      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.088     ; 3.379      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.088     ; 3.379      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.088     ; 3.379      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.086     ; 3.381      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.088     ; 3.379      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.088     ; 3.379      ;
; 63.187 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.088     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.188 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.379      ;
; 63.189 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.378      ;
; 63.189 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.087     ; 3.378      ;
; 65.426 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.140      ; 3.368      ;
; 65.426 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.369      ;
; 65.426 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.369      ;
; 65.426 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.369      ;
; 65.426 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.369      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.140      ; 3.367      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.142      ; 3.369      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.142      ; 3.369      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.142      ; 3.369      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.140      ; 3.367      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.140      ; 3.367      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.140      ; 3.367      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.142      ; 3.369      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.142      ; 3.369      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.142      ; 3.369      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.141      ; 3.368      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.140      ; 3.367      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.140      ; 3.367      ;
; 65.427 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.140      ; 3.367      ;
; 65.429 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.143      ; 3.368      ;
; 65.429 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.143      ; 3.368      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                             ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.633 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.373      ; 3.192      ;
; 0.633 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.373      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.371      ; 3.191      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.371      ; 3.191      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.371      ; 3.191      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.371      ; 3.191      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.371      ; 3.191      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.372      ; 3.192      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.371      ; 3.191      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.371      ; 3.191      ;
; 0.634 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.371      ; 3.191      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.933 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 3.202      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 3.202      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 3.202      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 3.202      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 3.202      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 3.202      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 3.204      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 3.202      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 3.202      ;
; 2.934 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 3.202      ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 1.012  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.267      ;
; 1.012  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.267      ;
; 1.012  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.267      ;
; 1.012  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.267      ;
; 1.496  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.737      ;
; 1.496  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.737      ;
; 1.496  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.055      ; 1.737      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.502  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 1.752      ;
; 1.504  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.759      ;
; 1.504  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.759      ;
; 1.504  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.759      ;
; 1.507  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.762      ;
; 1.507  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.762      ;
; 1.512  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.767      ;
; 1.512  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.767      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.517  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.772      ;
; 1.524  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.779      ;
; 1.524  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.779      ;
; 1.524  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.779      ;
; 1.524  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.779      ;
; 1.524  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.779      ;
; 1.524  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.779      ;
; 1.524  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.779      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.572  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.103      ; 1.861      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.731  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.104      ; 2.021      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.766  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 2.008      ;
; 1.945  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.200      ;
; 1.945  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.200      ;
; 1.945  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.200      ;
; 1.945  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.200      ;
; 2.017  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.272      ;
; 2.017  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.272      ;
; 2.017  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.272      ;
; 2.017  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.272      ;
; 2.375  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.067      ; 2.628      ;
; 2.391  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 2.645      ;
; 2.391  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 2.645      ;
; 2.391  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 2.645      ;
; 2.391  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 2.645      ;
; 2.625  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 2.879      ;
; 2.625  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 2.879      ;
; 2.625  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 2.879      ;
; 2.625  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 2.879      ;
; 51.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.321      ; 1.773      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                           ; To Node                                                                                                                                                                                                                ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a6 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 1.996      ;
; 1.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 1.996      ;
; 1.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 1.996      ;
; 1.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 1.996      ;
; 1.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 1.996      ;
; 1.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 1.996      ;
; 1.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 1.996      ;
; 1.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 2.070      ;
; 1.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 2.070      ;
; 1.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 2.070      ;
; 1.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 2.070      ;
; 1.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 2.070      ;
; 1.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 2.070      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a15   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a14   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a13   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a12   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a11   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a10   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a9    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a8    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a7    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a6    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a5    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a4    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a3    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a2    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.404      ; 2.582      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a55  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a54  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a53  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a52  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a51  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a50  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a49  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a48  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a47  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a46  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a45  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a44  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a43  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a42  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a41  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a40  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a39  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a38  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a37  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a36  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a23  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a22  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a21  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a20  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a19  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a18  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a17  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a16  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a7   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a6   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a5   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a4   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a3   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a2   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a1   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 2.590      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a63  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a62  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a61  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a60  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a59  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a58  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a57  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a56  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a35  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a34  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a33  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a32  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a31  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a30  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a29  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a28  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a27  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a26  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a25  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a24  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a15  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a14  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a13  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a12  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a11  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a10  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a9   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 2.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.406      ; 2.907      ;
; 4.341 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[1]                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.521      ; 5.048      ;
; 4.359 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.507      ; 5.052      ;
; 4.363 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.502      ; 5.051      ;
; 4.376 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[2]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.489      ; 5.051      ;
; 4.393 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.473      ; 5.052      ;
; 4.397 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.468      ; 5.051      ;
; 4.406 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.468      ; 5.060      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 2.671      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 2.671      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 2.671      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 2.670      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 2.670      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 2.672      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 2.672      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 2.686      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 2.686      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 2.672      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 2.686      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 2.686      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 2.677      ;
; 2.292 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 2.671      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.667      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.667      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.667      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.667      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.667      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.667      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.667      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 2.677      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.666      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.666      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.666      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.666      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.666      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.666      ;
; 2.293 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.666      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.667      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.667      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.667      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.667      ;
; 2.294 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.667      ;
; 2.296 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 2.684      ;
; 2.296 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 2.684      ;
; 2.296 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 2.684      ;
; 2.296 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 2.684      ;
; 2.296 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 2.684      ;
; 2.296 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 2.684      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.297 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 2.673      ;
; 2.545 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.825      ;
; 2.545 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.825      ;
; 2.546 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 2.825      ;
; 2.546 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 2.825      ;
; 2.546 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 2.825      ;
; 2.569 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.837      ;
; 2.664 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.044      ;
; 2.664 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.044      ;
; 2.664 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.044      ;
; 2.664 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.044      ;
; 2.664 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.044      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[2]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[3]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[4]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[6]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[5]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[7]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[8]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[9]   ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[0] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[1] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[2] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[3] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[4] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[5] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[6] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[7] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[8] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[9] ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[0]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[1]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[2]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[3]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[4]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[5]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[6]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[7]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[0]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[1]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[2]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[3]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[4]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[5]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[6]       ;
; 4.130 ; 4.350        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[7]       ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[0]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[1]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[2]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[3]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[4]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[5]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[6]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[7]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[0]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[1]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[2]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[3]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[4]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[5]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[6]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[7]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.271 ; 4.459        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.595 ; 5.815        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.601 ; 5.821        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.601 ; 5.821        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.601 ; 5.821        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.601 ; 5.821        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[6]                   ;
; 5.657 ; 5.815        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                       ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------+
; 17.336 ; 17.556       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]                                                    ;
; 17.336 ; 17.556       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[10]                                                   ;
; 17.336 ; 17.556       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[4]                                                    ;
; 17.338 ; 17.558       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[16]                                                   ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                        ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                        ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                        ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                    ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                    ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[11]                                                   ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                   ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[14]                                                   ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[15]                                                   ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[17]                                                   ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[3]                                                    ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[8]                                                    ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[9]                                                    ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_and                                                      ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_flip                                                     ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_less_than_or_equal                                       ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_or                                                       ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_store                                                    ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_u_less_than                                              ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_u_less_than_or_equal                                     ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_flip                                                 ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_push_sp                                              ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_and                                                  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_flip                                                 ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_push_sp                                              ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_u_less_than                                          ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_flip                                                 ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_push_sp                                              ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                        ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                        ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                        ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                        ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_dup_stk_b                                                ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_less_than                                                ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_and                                                  ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_dup_stk_b                                            ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_less_than                                            ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_less_than_or_equal                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_pop_down                                             ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_store                                                ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_u_less_than                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_u_less_than_or_equal                                 ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_dup_stk_b                                            ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_less_than                                            ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_less_than_or_equal                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_storeb                                               ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_u_less_than_or_equal                                 ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_and                                                  ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_dup_stk_b                                            ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_less_than                                            ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_less_than_or_equal                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_store                                                ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_storeb                                               ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_u_less_than                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_u_less_than_or_equal                                 ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[44] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[10]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[11]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[12]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[13]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[14]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[15]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[6]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[7]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[8]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_UG[9]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[13]                                                        ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[21]                                                        ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                        ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|ampl_U[0]                                                                                                 ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|ampl_U[1]                                                                                                 ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|ampl_U[2]                                                                                                 ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|ampl_U[3]                                                                                                 ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|ampl_U[4]                                                                                                 ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|ampl_U[5]                                                                                                 ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|ampl_U[6]                                                                                                 ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|ampl_U[7]                                                                                                 ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_mU[10]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_mU[11]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_mU[12]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_mU[13]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_mU[14]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_mU[15]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_mU[16]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_mU[9]                                                                                                ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_pU[10]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_pU[11]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_pU[12]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_pU[13]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_pU[14]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_pU[15]                                                                                               ;
; 17.346 ; 17.566       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|comp_pU[16]                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.604 ; 17.604       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.637 ; 17.637       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.642 ; 17.642       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.642 ; 17.642       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                            ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                       ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[0]              ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[1]              ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[2]              ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[3]              ;
; 33.042 ; 33.262       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus_buf1                 ;
; 33.042 ; 33.262       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus_buf2                 ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[0]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[1]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[2]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[3]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[4]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[5]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[6]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[7]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[8]       ;
; 33.043 ; 33.263       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[9]       ;
; 33.044 ; 33.264       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_out[3]             ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]                ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]              ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]              ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]              ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]              ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]              ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]              ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]              ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]              ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated          ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                 ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus~en                   ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus~reg0                 ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated          ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                 ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus_buf1                  ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus_buf2                  ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus~en                    ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus~reg0                  ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                  ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                  ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                  ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                  ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[0]           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[1]           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[2]           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[3]           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[4]           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[5]           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[6]           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[7]           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rden_sig                    ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid             ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                  ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch                       ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4           ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.end_send1      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send1          ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit0      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit1      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit2      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit3      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit4      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit5      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit6      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit7      ;
; 33.046 ; 33.266       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                         ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]                ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]                 ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                 ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                 ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle           ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.end_send2      ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_released ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start    ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send2          ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send3          ;
; 33.047 ; 33.267       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_complete  ;
; 33.050 ; 33.270       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[0]              ;
; 33.050 ; 33.270       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[1]              ;
; 33.050 ; 33.270       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[2]              ;
; 33.050 ; 33.270       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[3]              ;
; 33.050 ; 33.270       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[4]              ;
; 33.050 ; 33.270       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[5]              ;
; 33.050 ; 33.270       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[6]              ;
; 33.050 ; 33.270       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[7]              ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.485 ; 49.720       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.485 ; 49.720       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.488 ; 49.723       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.489 ; 49.724       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.489 ; 49.724       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.492 ; 49.727       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.542 ; 49.762       ; 0.220          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                 ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                      ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                      ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                      ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                      ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                             ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]                                                                                                                                       ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1]                                                                                                                                       ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2]                                                                                                                                       ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3]                                                                                                                                       ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                        ;
; 49.593 ; 49.781       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                        ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                    ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                          ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                          ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ;
; 49.594 ; 49.782       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 99.818  ; 99.818       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.850  ; 99.850       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.852  ; 99.852       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.147 ; 100.147      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.149 ; 100.149      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.182 ; 100.182      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.200 ; 100.200      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 100.200 ; 100.200      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 100.202 ; 100.202      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.202 ; 100.202      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                            ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; 2.724 ; 2.903 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.708 ; 2.887 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.717 ; 2.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.709 ; 2.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.708 ; 2.887 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.656 ; 2.834 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.717 ; 2.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.724 ; 2.903 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.718 ; 2.897 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.718 ; 2.897 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.718 ; 2.897 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; 3.255 ; 3.450 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.417 ; 1.590 ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 7.323 ; 7.455 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 4.216 ; 4.618 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 1.414 ; 1.833 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.594 ; 5.018 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 2.497 ; 2.903 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.752 ; 5.186 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 2.675 ; 3.105 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; -1.783 ; -1.961 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; -1.828 ; -2.007 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; -1.828 ; -2.007 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; -1.828 ; -2.007 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; -1.831 ; -2.010 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; -1.840 ; -2.019 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; -1.832 ; -2.011 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; -1.831 ; -2.010 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; -1.783 ; -1.961 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; -1.840 ; -2.019 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; -1.847 ; -2.026 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; -1.842 ; -2.021 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; -1.842 ; -2.021 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; -1.842 ; -2.021 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; -1.841 ; -2.020 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; -1.841 ; -2.020 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; -1.841 ; -2.020 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; -2.301 ; -2.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.667  ; 1.515  ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; -0.288 ; -0.398 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; -3.418 ; -3.809 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; -0.533 ; -0.929 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -3.782 ; -4.192 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -1.587 ; -1.980 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -3.863 ; -4.253 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -1.713 ; -2.130 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 5.688  ; 5.935  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 3.087  ; 2.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 3.087  ; 2.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 3.072  ; 2.859  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 2.251  ; 2.177  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 5.688  ; 5.935  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 3.073  ; 2.860  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 3.073  ; 2.860  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 5.701  ; 5.948  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 5.701  ; 5.948  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 2.264  ; 2.190  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 2.265  ; 2.191  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 3.085  ; 2.872  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 5.024  ; 5.448  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 5.024  ; 5.448  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 5.015  ; 5.439  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.410  ; 2.389  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 3.272  ; 3.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 3.086  ; 2.873  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 3.443  ; 3.298  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 5.008  ; 5.432  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 5.014  ; 5.438  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 3.442  ; 3.297  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 3.442  ; 3.297  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 3.086  ; 2.873  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 3.085  ; 2.872  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 5.703  ; 5.950  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 7.607  ; 7.993  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 4.347  ; 4.288  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 3.620  ; 3.528  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 3.505  ; 3.388  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 3.510  ; 3.604  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 11.898 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 12.246 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 4.868  ; 5.254  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 2.252  ; 2.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 4.868  ; 5.254  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 2.251  ; 2.177  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 2.254  ; 2.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 4.870  ; 5.256  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 4.870  ; 5.256  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 11.789 ; 12.749 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 5.760  ; 5.734  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 7.620  ; 7.614  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 8.887  ; 8.489  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 7.951  ; 7.983  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                            ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 1.524  ; 1.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 2.324  ; 2.116  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 2.324  ; 2.116  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 2.327  ; 2.119  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 2.327  ; 2.119  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 2.315  ; 2.107  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 2.315  ; 2.107  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 2.313  ; 2.105  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 1.524  ; 1.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 4.929  ; 5.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 2.314  ; 2.106  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 2.324  ; 2.116  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 2.314  ; 2.106  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 1.536  ; 1.462  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 4.941  ; 5.193  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 1.536  ; 1.462  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 1.538  ; 1.464  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 2.326  ; 2.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 1.683  ; 1.663  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.694  ; 2.556  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.694  ; 2.556  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.694  ; 2.556  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 4.297  ; 4.722  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 4.288  ; 4.713  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 1.683  ; 1.663  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.511  ; 2.364  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.326  ; 2.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.682  ; 2.544  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 4.281  ; 4.706  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.680  ; 2.542  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.680  ; 2.542  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.680  ; 2.542  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 4.287  ; 4.712  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.681  ; 2.543  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.681  ; 2.543  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 2.315  ; 2.107  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 2.326  ; 2.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 2.326  ; 2.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 4.943  ; 5.195  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 6.687  ; 7.073  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 3.453  ; 3.393  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 2.755  ; 2.663  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 2.644  ; 2.529  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 2.646  ; 2.740  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 11.109 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 11.459 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 1.524  ; 1.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 1.525  ; 1.451  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 4.141  ; 4.527  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 1.524  ; 1.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 1.527  ; 1.453  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 1.526  ; 1.452  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 1.526  ; 1.452  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 1.526  ; 1.452  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 1.526  ; 1.452  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 4.143  ; 4.529  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 9.496  ; 10.461 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 5.145  ; 5.120  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 6.923  ; 6.916  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 8.262  ; 7.862  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 7.240  ; 7.271  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.716 ; 3.640 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.716 ; 3.640 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.716 ; 3.640 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.716 ; 3.640 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.117 ; 6.478 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.118 ; 6.479 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.891 ; 3.805 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.901 ; 3.815 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.249 ; 4.101 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 5.076 ; 5.000 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 7.194 ; 7.555 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.395 ; 4.319 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.395 ; 4.319 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.395 ; 4.319 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.824 ; 7.185 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.394 ; 4.318 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.394 ; 4.318 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.634 ; 3.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.795 ; 5.719 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 8.037 ; 7.951 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 8.115 ; 8.476 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.828 ; 7.742 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.864 ; 2.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.864 ; 2.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.864 ; 2.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.864 ; 2.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.266 ; 5.627 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.267 ; 5.628 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.025 ; 2.939 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 2.948 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.332 ; 3.184 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.169 ; 4.093 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.299 ; 6.660 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.515 ; 3.439 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.515 ; 3.439 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.515 ; 3.439 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.944 ; 6.305 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.514 ; 3.438 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.514 ; 3.438 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.741 ; 2.593 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.186 ; 5.110 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.331 ; 7.245 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.510 ; 7.871 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.130 ; 7.044 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.641     ; 3.717     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.641     ; 3.717     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.641     ; 3.717     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.641     ; 3.717     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.473     ; 6.112     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.478     ; 6.117     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.805     ; 3.891     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.817     ; 3.903     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.064     ; 4.212     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.989     ; 5.065     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 7.552     ; 7.191     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.317     ; 4.393     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.317     ; 4.393     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.317     ; 4.393     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 7.182     ; 6.821     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.315     ; 4.391     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.315     ; 4.391     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.482     ; 3.630     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.704     ; 5.780     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.943     ; 8.029     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 8.504     ; 8.143     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.758     ; 7.844     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.788     ; 2.864     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.788     ; 2.864     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.788     ; 2.864     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.788     ; 2.864     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.622     ; 5.261     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.627     ; 5.266     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.938     ; 3.024     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.950     ; 3.036     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.149     ; 3.297     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.082     ; 4.158     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.658     ; 6.297     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.437     ; 3.513     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.437     ; 3.513     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.437     ; 3.513     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.303     ; 5.942     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.436     ; 3.512     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.436     ; 3.512     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.589     ; 2.737     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.096     ; 5.172     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.237     ; 7.323     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.898     ; 7.537     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.059     ; 7.145     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 52.24 MHz  ; 52.24 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 75.1 MHz   ; 75.1 MHz        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;      ;
; 137.59 MHz ; 137.59 MHz      ; altera_reserved_tck                                                           ;      ;
; 146.97 MHz ; 146.97 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 260.55 MHz ; 260.55 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                     ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -7.623 ; -828.251      ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.779  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.972  ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 26.675 ; 0.000         ;
; altera_reserved_tck                                                           ; 46.366 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.345 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.362 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.363 ; 0.000         ;
; altera_reserved_tck                                                           ; 0.363 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.406 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                  ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.370  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.482  ; 0.000         ;
; altera_reserved_tck                                                           ; 48.523 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 63.522 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.539 ; 0.000         ;
; altera_reserved_tck                                                           ; 0.915 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.290 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.057 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.129  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.596  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.322 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.589 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 32.984 ; 0.000         ;
; altera_reserved_tck                                                           ; 49.399 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.778 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                         ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                                                 ; Launch Clock                                         ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -7.623 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.096     ; 5.674      ;
; -7.617 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 5.669      ;
; -7.408 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.721     ; 5.834      ;
; -7.370 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.693     ; 5.824      ;
; -7.362 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 5.792      ;
; -7.306 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.721     ; 5.732      ;
; -7.302 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.679     ; 5.770      ;
; -7.296 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.756     ; 5.687      ;
; -7.244 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.724     ; 5.667      ;
; -7.218 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.696     ; 5.669      ;
; -7.201 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.693     ; 5.655      ;
; -7.175 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.682     ; 5.640      ;
; -7.169 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.724     ; 5.592      ;
; -7.162 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.107     ; 5.202      ;
; -7.143 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.696     ; 5.594      ;
; -7.111 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.759     ; 5.499      ;
; -7.106 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 5.536      ;
; -7.100 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.682     ; 5.565      ;
; -7.064 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.694     ; 5.517      ;
; -7.046 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.110     ; 5.083      ;
; -7.036 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.759     ; 5.424      ;
; -7.030 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.724     ; 5.453      ;
; -7.024 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.679     ; 5.492      ;
; -7.018 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 5.071      ;
; -7.013 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.692     ; 5.468      ;
; -7.008 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.693     ; 5.462      ;
; -7.004 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 5.057      ;
; -7.002 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 5.055      ;
; -6.987 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.692     ; 5.442      ;
; -6.971 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.110     ; 5.008      ;
; -6.960 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.081     ; 5.026      ;
; -6.958 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 5.015      ;
; -6.956 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 5.013      ;
; -6.955 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.724     ; 5.378      ;
; -6.939 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.760     ; 5.326      ;
; -6.939 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.760     ; 5.326      ;
; -6.929 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 4.986      ;
; -6.919 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 4.976      ;
; -6.909 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.085     ; 4.971      ;
; -6.874 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.927      ;
; -6.872 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.925      ;
; -6.864 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.760     ; 5.251      ;
; -6.864 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.760     ; 5.251      ;
; -6.856 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.701     ; 5.302      ;
; -6.834 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.085     ; 4.896      ;
; -6.832 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[2]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.099     ; 4.880      ;
; -6.829 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[2]   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.096     ; 4.880      ;
; -6.826 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.696     ; 5.277      ;
; -6.823 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.698     ; 5.272      ;
; -6.816 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.720     ; 5.243      ;
; -6.814 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 5.244      ;
; -6.814 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[1]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.103     ; 4.858      ;
; -6.803 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 4.860      ;
; -6.802 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.720     ; 5.229      ;
; -6.789 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[24] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.081     ; 4.855      ;
; -6.781 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.701     ; 5.227      ;
; -6.778 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.099     ; 4.826      ;
; -6.774 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 5.204      ;
; -6.770 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.693     ; 5.224      ;
; -6.751 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.696     ; 5.202      ;
; -6.741 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.720     ; 5.168      ;
; -6.739 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[1]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.103     ; 4.783      ;
; -6.735 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.099     ; 4.783      ;
; -6.733 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.082     ; 4.798      ;
; -6.729 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.692     ; 5.184      ;
; -6.729 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 4.786      ;
; -6.728 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.692     ; 5.183      ;
; -6.727 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.720     ; 5.154      ;
; -6.719 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.720     ; 5.146      ;
; -6.711 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.730     ; 5.128      ;
; -6.704 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.757      ;
; -6.703 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.099     ; 4.751      ;
; -6.700 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.751     ; 5.096      ;
; -6.700 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.753      ;
; -6.699 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.696     ; 5.150      ;
; -6.699 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.695     ; 5.151      ;
; -6.698 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 4.755      ;
; -6.697 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.695     ; 5.149      ;
; -6.696 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 4.753      ;
; -6.690 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.743      ;
; -6.689 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 5.119      ;
; -6.686 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.096     ; 4.737      ;
; -6.681 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 5.111      ;
; -6.667 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.682     ; 5.132      ;
; -6.662 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.696     ; 5.113      ;
; -6.660 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.099     ; 4.708      ;
; -6.658 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 4.715      ;
; -6.644 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.720     ; 5.071      ;
; -6.641 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.694      ;
; -6.633 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.696     ; 5.084      ;
; -6.624 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.695     ; 5.076      ;
; -6.622 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.695     ; 5.074      ;
; -6.609 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.110     ; 4.646      ;
; -6.601 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.682     ; 5.066      ;
; -6.598 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.720     ; 5.025      ;
; -6.595 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.090     ; 4.652      ;
; -6.587 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.696     ; 5.038      ;
; -6.574 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.627      ;
; -6.574 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.627      ;
; -6.566 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[21] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.698     ; 5.015      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.779 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.671     ;
; 0.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 10.688     ;
; 0.821 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 10.654     ;
; 0.831 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.619     ;
; 0.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 10.638     ;
; 0.841 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 10.645     ;
; 0.880 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 10.582     ;
; 0.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.575     ;
; 0.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 10.577     ;
; 0.917 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 10.558     ;
; 0.918 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.532     ;
; 0.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 10.541     ;
; 0.925 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 10.548     ;
; 0.929 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.519     ;
; 0.932 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 10.530     ;
; 0.939 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 10.525     ;
; 0.942 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.532     ;
; 0.944 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 10.531     ;
; 0.970 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.480     ;
; 0.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.467     ;
; 0.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 10.491     ;
; 0.996 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 10.477     ;
; 1.000 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 10.464     ;
; 1.018 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 10.445     ;
; 1.026 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.435     ;
; 1.045 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 10.418     ;
; 1.085 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 10.387     ;
; 1.096 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.378     ;
; 1.097 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.364     ;
; 1.102 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.372     ;
; 1.118 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 10.354     ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.328     ;
; 1.127 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.331     ;
; 1.134 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 10.338     ;
; 1.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 10.330     ;
; 1.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.296     ;
; 1.176 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.272     ;
; 1.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 10.279     ;
; 1.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.292     ;
; 1.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.274     ;
; 1.203 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 10.259     ;
; 1.205 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 10.258     ;
; 1.219 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.241     ;
; 1.219 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 10.267     ;
; 1.221 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 10.265     ;
; 1.222 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 10.242     ;
; 1.223 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 10.239     ;
; 1.225 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.249     ;
; 1.228 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.220     ;
; 1.235 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.225     ;
; 1.237 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 10.234     ;
; 1.244 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.217     ;
; 1.255 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 10.207     ;
; 1.261 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.189     ;
; 1.272 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.176     ;
; 1.275 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.571     ; 9.788      ;
; 1.283 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.147     ; 10.204     ;
; 1.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 10.181     ;
; 1.284 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.196     ;
; 1.293 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 10.157     ;
; 1.301 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 10.148     ;
; 1.301 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 10.162     ;
; 1.304 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.144     ;
; 1.309 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.152     ;
; 1.320 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.154     ;
; 1.322 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.152     ;
; 1.328 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 10.135     ;
; 1.338 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.121     ;
; 1.339 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 10.139     ;
; 1.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 10.096     ;
; 1.361 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.113     ;
; 1.376 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.583     ; 9.675      ;
; 1.379 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.095     ;
; 1.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.081     ;
; 1.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 10.093     ;
; 1.384 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 10.091     ;
; 1.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 10.083     ;
; 1.405 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 10.057     ;
; 1.414 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 10.064     ;
; 1.435 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.039     ;
; 1.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.026     ;
; 1.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 10.018     ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 10.005     ;
; 1.462 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 10.000     ;
; 1.469 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 9.991      ;
; 1.470 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.988      ;
; 1.472 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 10.014     ;
; 1.480 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 9.999      ;
; 1.483 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 9.980      ;
; 1.484 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 9.964      ;
; 1.486 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 9.976      ;
; 1.495 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 9.980      ;
; 1.502 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 9.956      ;
; 1.502 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 9.958      ;
; 1.507 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 9.972      ;
; 1.512 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 9.964      ;
; 1.515 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 9.951      ;
; 1.515 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 9.971      ;
; 1.518 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 9.942      ;
; 1.519 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 9.929      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                          ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.972 ; svideo_yout_dly2[6]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.648      ;
; 4.976 ; svideo_yout_dly2[5]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.644      ;
; 4.993 ; svideo_yout_dly2[6]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.629      ;
; 4.994 ; svideo_yout_dly2[5]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.628      ;
; 5.013 ; svideo_yout_dly2[6]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.607      ;
; 5.017 ; svideo_yout_dly2[5]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.603      ;
; 5.051 ; svideo_yout_dly2[5]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.571      ;
; 5.053 ; svideo_yout_dly2[6]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.569      ;
; 5.077 ; svideo_yout_dly2[5]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.545      ;
; 5.079 ; svideo_yout_dly2[6]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.543      ;
; 5.124 ; svideo_yout_dly2[6]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.497      ;
; 5.128 ; svideo_yout_dly2[5]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.493      ;
; 5.241 ; svideo_yout_dly2[4]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.379      ;
; 5.262 ; svideo_yout_dly2[4]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.360      ;
; 5.272 ; svideo_yout_dly2[7]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.350      ;
; 5.280 ; svideo_yout_dly2[7]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.340      ;
; 5.282 ; svideo_yout_dly2[4]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.338      ;
; 5.289 ; svideo_yout_dly2[6]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.333      ;
; 5.293 ; svideo_yout_dly2[5]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.329      ;
; 5.329 ; svideo_yout_dly2[7]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.293      ;
; 5.330 ; svideo_yout_dly2[7]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.290      ;
; 5.337 ; svideo_yout_dly2[4]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.285      ;
; 5.355 ; svideo_yout_dly2[7]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.267      ;
; 5.364 ; svideo_yout_dly2[4]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.258      ;
; 5.393 ; svideo_yout_dly2[4]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.228      ;
; 5.449 ; svideo_yout_dly2[3]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.171      ;
; 5.451 ; svideo_yout_dly2[6]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.170      ;
; 5.455 ; svideo_yout_dly2[5]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.166      ;
; 5.460 ; svideo_yout_dly2[7]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.161      ;
; 5.470 ; svideo_yout_dly2[3]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.152      ;
; 5.489 ; svideo_yout_dly2[2]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.133      ;
; 5.490 ; svideo_yout_dly2[3]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.130      ;
; 5.497 ; svideo_yout_dly2[2]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.123      ;
; 5.542 ; svideo_yout_dly2[1]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.078      ;
; 5.545 ; svideo_yout_dly2[3]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.077      ;
; 5.546 ; svideo_yout_dly2[2]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.076      ;
; 5.547 ; svideo_yout_dly2[2]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.073      ;
; 5.558 ; svideo_yout_dly2[4]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.064      ;
; 5.563 ; svideo_yout_dly2[1]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.059      ;
; 5.572 ; svideo_yout_dly2[2]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.050      ;
; 5.572 ; svideo_yout_dly2[3]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.050      ;
; 5.583 ; svideo_yout_dly2[1]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.037      ;
; 5.601 ; svideo_yout_dly2[3]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.020      ;
; 5.602 ; svideo_yout_dly2[7]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.020      ;
; 5.638 ; svideo_yout_dly2[1]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.984      ;
; 5.665 ; svideo_yout_dly2[1]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.957      ;
; 5.671 ; svideo_yout_dly2[2]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.950      ;
; 5.694 ; svideo_yout_dly2[1]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.927      ;
; 5.720 ; svideo_yout_dly2[4]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.901      ;
; 5.766 ; svideo_yout_dly2[3]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.856      ;
; 5.787 ; svideo_yout_dly2[7]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.834      ;
; 5.810 ; svideo_yout_dly2[0]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.812      ;
; 5.818 ; svideo_yout_dly2[0]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 2.802      ;
; 5.819 ; svideo_yout_dly2[2]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.803      ;
; 5.859 ; svideo_yout_dly2[1]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.763      ;
; 5.867 ; svideo_yout_dly2[0]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.755      ;
; 5.868 ; svideo_yout_dly2[0]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 2.752      ;
; 5.893 ; svideo_yout_dly2[0]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.729      ;
; 5.928 ; svideo_yout_dly2[3]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.693      ;
; 5.998 ; svideo_yout_dly2[2]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.623      ;
; 6.007 ; svideo_yout_dly2[0]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.614      ;
; 6.021 ; svideo_yout_dly2[1]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.600      ;
; 6.140 ; svideo_yout_dly2[0]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.482      ;
; 6.334 ; svideo_yout_dly2[0]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 2.287      ;
; 6.337 ; svideo:svideo|luma[2]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.313      ;
; 6.345 ; svideo:svideo|chroma[0] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.305      ;
; 6.353 ; cvbs1_out[3]            ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.072     ; 2.272      ;
; 6.358 ; svideo:svideo|luma[1]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.160     ; 2.291      ;
; 6.360 ; svideo:svideo|luma[0]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.160     ; 2.289      ;
; 6.362 ; cvbs1_out[4]            ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.072     ; 2.263      ;
; 6.387 ; svideo:svideo|luma[1]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.160     ; 2.262      ;
; 6.389 ; svideo:svideo|luma[0]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.160     ; 2.260      ;
; 6.436 ; cvbs1_out[9]            ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.072     ; 2.189      ;
; 6.437 ; svideo:svideo|chroma[1] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.213      ;
; 6.439 ; svideo:svideo|chroma[2] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.211      ;
; 6.453 ; svideo:svideo|luma[2]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.197      ;
; 6.461 ; svideo:svideo|chroma[0] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.189      ;
; 6.464 ; svideo:svideo|luma[4]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.186      ;
; 6.466 ; svideo:svideo|chroma[1] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.184      ;
; 6.474 ; svideo:svideo|luma[1]   ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.160     ; 2.175      ;
; 6.476 ; svideo:svideo|luma[0]   ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.160     ; 2.173      ;
; 6.482 ; svideo:svideo|luma[2]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.168      ;
; 6.490 ; svideo:svideo|chroma[0] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.160      ;
; 6.499 ; svideo:svideo|chroma[3] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.151      ;
; 6.503 ; svideo:svideo|luma[1]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.160     ; 2.146      ;
; 6.505 ; svideo:svideo|luma[0]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.160     ; 2.144      ;
; 6.518 ; svideo:svideo|luma[3]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.132      ;
; 6.522 ; cvbs1_out[2]            ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.072     ; 2.103      ;
; 6.524 ; svideo:svideo|chroma[3] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.126      ;
; 6.542 ; svideo:svideo|luma[3]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.108      ;
; 6.543 ; svideo:svideo|luma_2[1] ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.062     ; 2.204      ;
; 6.553 ; svideo:svideo|chroma[1] ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.097      ;
; 6.555 ; svideo:svideo|chroma[2] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.095      ;
; 6.569 ; svideo:svideo|luma[2]   ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.081      ;
; 6.572 ; svideo:svideo|luma_2[1] ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.062     ; 2.175      ;
; 6.577 ; svideo:svideo|chroma[0] ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.073      ;
; 6.580 ; svideo:svideo|luma[4]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.070      ;
; 6.582 ; svideo:svideo|chroma[1] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.068      ;
; 6.584 ; svideo:svideo|chroma[4] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.066      ;
; 6.584 ; svideo:svideo|chroma[2] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.159     ; 2.066      ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                              ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                     ; To Node                                                         ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 26.675 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.557      ;
; 26.675 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.557      ;
; 26.696 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.536      ;
; 26.696 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.536      ;
; 26.721 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 6.477      ;
; 26.721 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 6.477      ;
; 26.757 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.475      ;
; 26.757 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.475      ;
; 26.778 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.454      ;
; 26.778 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.454      ;
; 26.859 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 6.339      ;
; 26.859 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 6.339      ;
; 26.882 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.350      ;
; 26.882 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.350      ;
; 26.964 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.268      ;
; 26.964 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.268      ;
; 26.997 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.235      ;
; 26.997 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.235      ;
; 27.052 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.180      ;
; 27.052 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.180      ;
; 27.079 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.153      ;
; 27.079 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.153      ;
; 27.134 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.098      ;
; 27.134 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.098      ;
; 27.170 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 6.028      ;
; 27.170 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 6.028      ;
; 27.180 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.052      ;
; 27.180 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 6.052      ;
; 27.241 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.987      ;
; 27.253 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.975      ;
; 27.262 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 5.970      ;
; 27.262 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 5.970      ;
; 27.318 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.910      ;
; 27.330 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.898      ;
; 27.371 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.827      ;
; 27.371 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.827      ;
; 27.389 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.809      ;
; 27.389 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.809      ;
; 27.464 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.764      ;
; 27.480 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[0]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.138     ; 5.704      ;
; 27.482 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.746      ;
; 27.485 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.743      ;
; 27.507 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[9]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.137     ; 5.678      ;
; 27.507 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.137     ; 5.678      ;
; 27.556 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.672      ;
; 27.571 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.657      ;
; 27.579 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.649      ;
; 27.581 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.647      ;
; 27.582 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.646      ;
; 27.583 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.645      ;
; 27.584 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.644      ;
; 27.590 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 5.642      ;
; 27.590 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 5.642      ;
; 27.592 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.636      ;
; 27.600 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.628      ;
; 27.602 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.626      ;
; 27.602 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.626      ;
; 27.603 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.625      ;
; 27.604 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.624      ;
; 27.605 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.623      ;
; 27.611 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 5.621      ;
; 27.611 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.090     ; 5.621      ;
; 27.618 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[0]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.138     ; 5.566      ;
; 27.630 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.598      ;
; 27.645 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.583      ;
; 27.651 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.577      ;
; 27.655 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.543      ;
; 27.655 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.543      ;
; 27.671 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.557      ;
; 27.671 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.557      ;
; 27.712 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.486      ;
; 27.712 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.486      ;
; 27.722 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.506      ;
; 27.732 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.466      ;
; 27.732 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.124     ; 5.466      ;
; 27.762 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.466      ;
; 27.762 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.466      ;
; 27.764 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.464      ;
; 27.767 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[12]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.461      ;
; 27.768 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[4]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.123     ; 5.431      ;
; 27.768 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[6]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.123     ; 5.431      ;
; 27.769 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.459      ;
; 27.770 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.458      ;
; 27.778 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.450      ;
; 27.783 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.445      ;
; 27.784 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.444      ;
; 27.785 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.443      ;
; 27.786 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.442      ;
; 27.786 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.442      ;
; 27.788 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.440      ;
; 27.788 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[12]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.440      ;
; 27.789 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.439      ;
; 27.790 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.438      ;
; 27.790 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.438      ;
; 27.791 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.437      ;
; 27.791 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.094     ; 5.437      ;
; 27.795 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.136     ; 5.391      ;
; 27.795 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.136     ; 5.391      ;
; 27.795 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.136     ; 5.391      ;
; 27.795 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.136     ; 5.391      ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                             ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 46.366 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.225      ; 3.858      ;
; 46.379 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.226      ; 3.846      ;
; 46.521 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.225      ; 3.703      ;
; 46.822 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.269      ; 3.446      ;
; 46.889 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.254      ; 3.364      ;
; 47.066 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.254      ; 3.187      ;
; 47.072 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.256      ; 3.183      ;
; 47.080 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.256      ; 3.175      ;
; 47.096 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.225      ; 3.128      ;
; 47.179 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.257      ; 3.077      ;
; 47.210 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.254      ; 3.043      ;
; 47.211 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.254      ; 3.042      ;
; 47.276 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.256      ; 2.979      ;
; 47.296 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.256      ; 2.959      ;
; 47.483 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.254      ; 2.770      ;
; 47.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.225      ; 2.695      ;
; 47.574 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.253      ; 2.678      ;
; 47.574 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.257      ; 2.682      ;
; 47.665 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.253      ; 2.587      ;
; 47.706 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.267      ; 2.560      ;
; 47.777 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.254      ; 2.476      ;
; 47.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.253      ; 2.353      ;
; 48.265 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.253      ; 1.987      ;
; 48.307 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.256      ; 1.948      ;
; 95.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.871      ;
; 95.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.871      ;
; 95.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.871      ;
; 95.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.871      ;
; 95.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.871      ;
; 95.418 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.312     ; 4.269      ;
; 95.435 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.312     ; 4.252      ;
; 95.490 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.312     ; 4.197      ;
; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.403      ;
; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.403      ;
; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.403      ;
; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.403      ;
; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.403      ;
; 95.544 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.312     ; 4.143      ;
; 95.566 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.312     ; 4.121      ;
; 95.569 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.312     ; 4.118      ;
; 95.570 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 4.364      ;
; 95.570 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 4.364      ;
; 95.570 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 4.364      ;
; 95.570 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 4.364      ;
; 95.570 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 4.364      ;
; 95.600 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.312     ; 4.087      ;
; 95.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.275      ;
; 95.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.275      ;
; 95.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.275      ;
; 95.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.275      ;
; 95.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 4.275      ;
; 95.708 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.227      ;
; 95.708 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.227      ;
; 95.708 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.227      ;
; 95.708 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.227      ;
; 95.708 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.227      ;
; 95.731 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.957      ;
; 95.738 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.950      ;
; 95.772 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.916      ;
; 95.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.128      ;
; 95.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.128      ;
; 95.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.128      ;
; 95.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.128      ;
; 95.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 4.128      ;
; 95.854 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.834      ;
; 95.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.106     ; 4.036      ;
; 95.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.106     ; 4.036      ;
; 95.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.106     ; 4.036      ;
; 95.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.106     ; 4.036      ;
; 95.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.106     ; 4.036      ;
; 95.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.106     ; 4.036      ;
; 95.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.106     ; 4.036      ;
; 95.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.106     ; 4.036      ;
; 95.860 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.312     ; 3.827      ;
; 95.866 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.822      ;
; 95.874 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.814      ;
; 95.878 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.810      ;
; 95.879 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.809      ;
; 95.913 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 4.024      ;
; 95.913 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 4.024      ;
; 95.913 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 4.024      ;
; 95.913 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 4.024      ;
; 95.984 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.952      ;
; 95.984 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.952      ;
; 95.984 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.952      ;
; 95.984 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.952      ;
; 95.984 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.952      ;
; 95.984 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.952      ;
; 95.984 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.952      ;
; 95.984 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.952      ;
; 96.025 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 3.910      ;
; 96.025 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 3.910      ;
; 96.025 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 3.910      ;
; 96.025 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 3.910      ;
; 96.025 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 3.910      ;
; 96.037 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 3.896      ;
; 96.037 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 3.896      ;
; 96.037 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 3.896      ;
; 96.037 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 3.896      ;
; 96.037 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 3.896      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                  ; To Node                                                                                                                                                                                                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.345 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[2]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.934      ;
; 0.347 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.597      ;
; 0.348 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 0.597      ;
; 0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 0.597      ;
; 0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.937      ;
; 0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[1]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.937      ;
; 0.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.938      ;
; 0.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[2]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.940      ;
; 0.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[5]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.939      ;
; 0.352 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[3]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.941      ;
; 0.352 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.941      ;
; 0.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.942      ;
; 0.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[5]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.942      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[7]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.943      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[3]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 0.944      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[6]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.943      ;
; 0.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.945      ;
; 0.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[2]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.947      ;
; 0.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.946      ;
; 0.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 0.948      ;
; 0.359 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_raw_reg[1]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.950      ;
; 0.360 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.951      ;
; 0.360 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[4]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 0.950      ;
; 0.361 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[3]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.950      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                                                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf1_reg[5]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf1_reg[5]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf1_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf1_reg[0]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[4]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[4]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[0]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[1]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[6]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                                                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[2]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[1]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[1]                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[2]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[2]                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[3]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[3]                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[0]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[3]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[3]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_clock_reg                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_clock_reg                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[3]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[3]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[4]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[4]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[7]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[1]                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[1]                                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[1]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[1]                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[3]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[3]                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[2]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[2]                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                           ; To Node                                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.362 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[6]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[6]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack_end            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack_end            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1_end  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait30                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait30                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait40                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait40                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid                    ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[1]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[7]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[7]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[4]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[4]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[5]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[5]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[0]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp_previous                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm_previous                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; cntr_reset[1]                                                       ; cntr_reset[1]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; cntr_reset[2]                                                       ; cntr_reset[2]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; cntr_reset[5]                                                       ; cntr_reset[5]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; cntr_reset[6]                                                       ; cntr_reset[6]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; reset_usbdrv                                                        ; reset_usbdrv                                                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start           ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_idle            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_idle            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.start_get_data          ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.start_get_data          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|detach_ack                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|detach_ack                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_state         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_state         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_for_deviceconnect  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_for_deviceconnect  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[0]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[0]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.363 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.374 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.608      ;
; 0.450 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dq_oe             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.684      ;
; 0.486 ; seq_reg[0]                                                                                                      ; seq_reg[1]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.719      ;
; 0.540 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.774      ;
; 0.542 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.776      ;
; 0.554 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.788      ;
; 0.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 0.901      ;
; 0.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 0.901      ;
; 0.581 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.815      ;
; 0.584 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.818      ;
; 0.586 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.819      ;
; 0.588 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.822      ;
; 0.588 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.822      ;
; 0.589 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.823      ;
; 0.592 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.826      ;
; 0.592 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.826      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.827      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.827      ;
; 0.594 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.828      ;
; 0.594 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.828      ;
; 0.599 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.832      ;
; 0.608 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.842      ;
; 0.612 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.846      ;
; 0.614 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.848      ;
; 0.619 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.852      ;
; 0.623 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.856      ;
; 0.629 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.862      ;
; 0.637 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.871      ;
; 0.686 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.018      ;
; 0.690 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.022      ;
; 0.714 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.947      ;
; 0.743 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.976      ;
; 0.746 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]  ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.078      ;
; 0.753 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.986      ;
; 0.774 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.106      ;
; 0.775 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.107      ;
; 0.776 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.108      ;
; 0.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 1.119      ;
; 0.780 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.112      ;
; 0.784 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.018      ;
; 0.788 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.120      ;
; 0.797 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.030      ;
; 0.815 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]  ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.147      ;
; 0.826 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 1.168      ;
; 0.838 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.072      ;
; 0.864 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 1.206      ;
; 0.873 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.205      ;
; 0.874 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.108      ;
; 0.874 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.108      ;
; 0.877 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.111      ;
; 0.879 ; sdram_request_reg                                                                                               ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.113      ;
; 0.879 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.113      ;
; 0.879 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.113      ;
; 0.880 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.114      ;
; 0.881 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.115      ;
; 0.881 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.115      ;
; 0.882 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.116      ;
; 0.888 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.122      ;
; 0.889 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.123      ;
; 0.891 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.125      ;
; 0.892 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.126      ;
; 0.892 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.126      ;
; 0.893 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.127      ;
; 0.924 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.158      ;
; 0.929 ; sdram_ctrl:sdram_controller|r_rddata[4]                                                                         ; ram_do_reg[20]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.212      ; 1.312      ;
; 0.936 ; sdram_ctrl:sdram_controller|r_rddata[1]                                                                         ; ram_do_reg[17]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 1.307      ;
; 0.938 ; sdram_ctrl:sdram_controller|r_rddata[2]                                                                         ; ram_do_reg[18]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 1.309      ;
; 0.939 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.172      ;
; 0.939 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.173      ;
; 0.948 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.280      ;
; 0.961 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.195      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.207      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.207      ;
; 0.978 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.212      ;
; 0.982 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.215      ;
; 0.984 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.218      ;
; 0.984 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.218      ;
; 0.987 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.221      ;
; 0.989 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.223      ;
; 0.990 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.224      ;
; 0.991 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.225      ;
; 0.991 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.225      ;
; 0.991 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]  ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.323      ;
; 0.998 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.232      ;
; 1.001 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.235      ;
; 1.002 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.236      ;
; 1.002 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.236      ;
; 1.014 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.346      ;
; 1.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]  ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.351      ;
; 1.030 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.263      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                             ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.364 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.597      ;
; 0.374 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.608      ;
; 0.374 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.608      ;
; 0.375 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.608      ;
; 0.390 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.624      ;
; 0.394 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.628      ;
; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.630      ;
; 0.397 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.631      ;
; 0.398 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.632      ;
; 0.398 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.632      ;
; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.638      ;
; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.638      ;
; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.639      ;
; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.639      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.406 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.640      ;
; 0.406 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.640      ;
; 0.406 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.639      ;
; 0.407 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.641      ;
; 0.407 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.640      ;
; 0.407 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.642      ;
; 0.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.643      ;
; 0.409 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.643      ;
; 0.409 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.643      ;
; 0.410 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.643      ;
; 0.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.644      ;
; 0.410 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.644      ;
; 0.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.645      ;
; 0.411 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.644      ;
; 0.411 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.644      ;
; 0.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.645      ;
; 0.411 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.645      ;
; 0.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.646      ;
; 0.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.646      ;
; 0.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.646      ;
; 0.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.646      ;
; 0.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.646      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.649      ;
; 0.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.656      ;
; 0.423 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.657      ;
; 0.424 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.659      ;
; 0.425 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.659      ;
; 0.425 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.659      ;
; 0.426 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.660      ;
; 0.426 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.660      ;
; 0.426 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.659      ;
; 0.426 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.659      ;
; 0.426 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 0.659      ;
; 0.426 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.660      ;
; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.662      ;
; 0.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.673      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.675      ;
; 0.464 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 0.982      ;
; 0.468 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.315      ; 0.984      ;
; 0.474 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.315      ; 0.990      ;
; 0.476 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.315      ; 0.992      ;
; 0.477 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 0.995      ;
; 0.499 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 1.017      ;
; 0.504 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 1.022      ;
; 0.510 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 1.028      ;
; 0.516 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.750      ;
; 0.516 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.750      ;
; 0.516 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.750      ;
; 0.516 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.315      ; 1.032      ;
; 0.517 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.751      ;
; 0.518 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.752      ;
; 0.518 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.315      ; 1.034      ;
; 0.519 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.753      ;
; 0.524 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.758      ;
; 0.530 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 1.048      ;
; 0.532 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 1.050      ;
; 0.535 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.769      ;
; 0.536 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.770      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                             ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                 ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.406 ; svideo:svideo|luma_acc[9] ; svideo_yout_dly1[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.639      ;
; 0.407 ; svideo:svideo|luma_acc[4] ; svideo_yout_dly1[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.640      ;
; 0.408 ; svideo_yout_dly1[3]       ; svideo_yout_dly2[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.641      ;
; 0.409 ; svideo_yout_dly1[5]       ; svideo_yout_dly2[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.642      ;
; 0.465 ; svideo:svideo|luma[6]     ; svideo:svideo|luma_1[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.796      ;
; 0.513 ; svideo:svideo|luma[5]     ; svideo:svideo|luma_1[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.844      ;
; 0.518 ; svideo:svideo|luma[7]     ; svideo:svideo|luma_1[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.849      ;
; 0.518 ; svideo:svideo|luma[9]     ; svideo:svideo|luma_1[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.849      ;
; 0.551 ; svideo_yout_dly1[6]       ; svideo_yout_dly2[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.065      ; 0.787      ;
; 0.551 ; svideo:svideo|luma_acc[3] ; svideo_yout_dly1[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.784      ;
; 0.552 ; svideo:svideo|luma_acc[6] ; svideo_yout_dly1[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.785      ;
; 0.554 ; svideo:svideo|luma_2[9]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.787      ;
; 0.560 ; svideo:svideo|luma_acc[8] ; svideo_yout_dly1[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.793      ;
; 0.561 ; svideo_yout_dly1[0]       ; svideo_yout_dly2[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.794      ;
; 0.563 ; svideo:svideo|luma_1[3]   ; svideo:svideo|luma_2[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.797      ;
; 0.579 ; svideo:svideo|luma_1[2]   ; svideo:svideo|luma_2[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.813      ;
; 0.580 ; svideo:svideo|luma_1[5]   ; svideo:svideo|luma_2[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.814      ;
; 0.583 ; svideo:svideo|luma_1[0]   ; svideo:svideo|luma_2[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.817      ;
; 0.591 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.824      ;
; 0.594 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.827      ;
; 0.594 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.827      ;
; 0.597 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.830      ;
; 0.609 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.842      ;
; 0.659 ; svideo:svideo|chroma[8]   ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 0.992      ;
; 0.664 ; svideo:svideo|luma[6]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.995      ;
; 0.676 ; svideo:svideo|luma[7]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.141      ; 1.006      ;
; 0.677 ; svideo:svideo|luma[9]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.141      ; 1.007      ;
; 0.712 ; svideo:svideo|luma[5]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.141      ; 1.042      ;
; 0.715 ; svideo:svideo|luma[0]     ; svideo:svideo|luma_1[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.046      ;
; 0.720 ; svideo:svideo|luma[3]     ; svideo:svideo|luma_1[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.143      ; 1.052      ;
; 0.720 ; svideo:svideo|luma_1[9]   ; svideo:svideo|luma_2[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.954      ;
; 0.722 ; svideo:svideo|luma_1[8]   ; svideo:svideo|luma_2[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.956      ;
; 0.724 ; svideo:svideo|luma[1]     ; svideo:svideo|luma_1[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.055      ;
; 0.731 ; svideo:svideo|luma[2]     ; svideo:svideo|luma_1[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.143      ; 1.063      ;
; 0.733 ; svideo:svideo|luma_acc[7] ; svideo_yout_dly1[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.064      ; 0.968      ;
; 0.740 ; svideo:svideo|luma[0]     ; luma_saturated[0]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.071      ;
; 0.741 ; luma_saturated[3]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.974      ;
; 0.746 ; svideo:svideo|luma_1[1]   ; svideo:svideo|luma_2[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.980      ;
; 0.752 ; luma_saturated[6]         ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.985      ;
; 0.753 ; luma_saturated[2]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.986      ;
; 0.754 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.988      ;
; 0.758 ; svideo:svideo|luma_1[6]   ; svideo:svideo|luma_2[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.992      ;
; 0.760 ; svideo:svideo|luma_1[7]   ; svideo:svideo|luma_2[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 0.994      ;
; 0.762 ; svideo_yout_dly1[1]       ; svideo_yout_dly2[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.065      ; 0.998      ;
; 0.764 ; svideo_yout_dly1[4]       ; svideo_yout_dly2[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.065      ; 1.000      ;
; 0.769 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 1.003      ;
; 0.780 ; luma_saturated[9]         ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.013      ;
; 0.785 ; luma_saturated[4]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.018      ;
; 0.787 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 1.021      ;
; 0.788 ; luma_saturated[5]         ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.021      ;
; 0.792 ; luma_saturated[7]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.025      ;
; 0.799 ; svideo:svideo|luma_2[3]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 1.033      ;
; 0.801 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 1.035      ;
; 0.833 ; svideo:svideo|chroma[4]   ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 1.166      ;
; 0.840 ; svideo:svideo|chroma[6]   ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 1.173      ;
; 0.864 ; svideo:svideo|chroma[7]   ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 1.197      ;
; 0.864 ; svideo:svideo|chroma[2]   ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 1.197      ;
; 0.866 ; svideo:svideo|chroma[8]   ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 1.199      ;
; 0.877 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.110      ;
; 0.879 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.112      ;
; 0.881 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.114      ;
; 0.882 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.115      ;
; 0.885 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.118      ;
; 0.890 ; svideo:svideo|chroma[5]   ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 1.223      ;
; 0.893 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.126      ;
; 0.896 ; svideo:svideo|chroma[3]   ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 1.229      ;
; 0.901 ; svideo:svideo|luma[4]     ; svideo:svideo|luma_1[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.143      ; 1.233      ;
; 0.919 ; svideo:svideo|luma_acc[2] ; svideo_yout_dly1[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.064      ; 1.154      ;
; 0.921 ; svideo:svideo|luma[3]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.143      ; 1.253      ;
; 0.921 ; svideo:svideo|luma[8]     ; svideo:svideo|luma_1[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.144      ; 1.254      ;
; 0.922 ; svideo_yout_dly1[7]       ; svideo_yout_dly2[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.064      ; 1.157      ;
; 0.924 ; svideo:svideo|luma_1[4]   ; svideo:svideo|luma_2[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 1.158      ;
; 0.925 ; svideo:svideo|luma[0]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.256      ;
; 0.926 ; svideo_yout_dly1[2]       ; svideo_yout_dly2[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.064      ; 1.161      ;
; 0.931 ; svideo:svideo|luma[4]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.143      ; 1.263      ;
; 0.933 ; svideo:svideo|luma_acc[5] ; svideo_yout_dly1[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.064      ; 1.168      ;
; 0.935 ; svideo:svideo|luma[1]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.266      ;
; 0.938 ; svideo:svideo|luma[8]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.143      ; 1.270      ;
; 0.941 ; svideo:svideo|luma[2]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.143      ; 1.273      ;
; 0.944 ; svideo:svideo|luma_2[1]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 1.178      ;
; 0.949 ; svideo:svideo|luma[6]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.280      ;
; 0.949 ; luma_saturated[8]         ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.182      ;
; 0.957 ; svideo:svideo|luma[7]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.141      ; 1.287      ;
; 0.976 ; svideo:svideo|luma[7]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.141      ; 1.306      ;
; 0.976 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.209      ;
; 0.978 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.211      ;
; 0.980 ; svideo:svideo|luma[5]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.141      ; 1.310      ;
; 0.980 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.213      ;
; 0.987 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.220      ;
; 0.989 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.222      ;
; 0.992 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.225      ;
; 1.003 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.236      ;
; 1.012 ; svideo:svideo|luma[5]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.141      ; 1.342      ;
; 1.019 ; luma_saturated[2]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.252      ;
; 1.023 ; svideo:svideo|luma[6]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.354      ;
; 1.026 ; luma_saturated[3]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.259      ;
; 1.032 ; luma_saturated[1]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.265      ;
; 1.034 ; luma_saturated[6]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.267      ;
; 1.040 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 1.274      ;
; 1.041 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.063      ; 1.275      ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                              ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 5.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.144     ; 6.233      ;
; 5.416 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 6.184      ;
; 5.416 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 6.184      ;
; 5.416 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 6.184      ;
; 5.416 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 6.184      ;
; 5.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.133     ; 6.193      ;
; 5.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.133     ; 6.193      ;
; 5.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.133     ; 6.193      ;
; 5.756 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.834      ;
; 5.756 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.834      ;
; 5.756 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 5.834      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 5.847      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[21] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 5.851      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.757 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 5.848      ;
; 5.758 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 5.844      ;
; 5.758 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 5.844      ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                  ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 8.482 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.241     ; 2.906      ;
; 8.546 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 2.919      ;
; 8.546 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 2.920      ;
; 8.546 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 2.920      ;
; 8.547 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.920      ;
; 8.547 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.920      ;
; 8.547 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 2.918      ;
; 8.547 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 2.918      ;
; 8.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.296     ; 2.775      ;
; 8.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.303     ; 2.768      ;
; 8.560 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.297     ; 2.770      ;
; 8.560 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.297     ; 2.770      ;
; 8.560 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.297     ; 2.770      ;
; 8.560 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.299     ; 2.768      ;
; 8.560 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.299     ; 2.768      ;
; 8.560 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.299     ; 2.768      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.908      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.908      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.908      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.908      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.908      ;
; 8.569 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.910      ;
; 8.569 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.910      ;
; 8.569 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.909      ;
; 8.572 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 2.875      ;
; 8.572 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.868      ;
; 8.573 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.297     ; 2.757      ;
; 8.576 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.290     ; 2.761      ;
; 8.576 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 2.868      ;
; 8.576 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 2.868      ;
; 8.576 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 2.868      ;
; 8.576 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.870      ;
; 8.576 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.870      ;
; 8.576 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.870      ;
; 8.577 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.285     ; 2.765      ;
; 8.577 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.288     ; 2.762      ;
; 8.577 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.285     ; 2.765      ;
; 8.577 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.285     ; 2.765      ;
; 8.580 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.288     ; 2.759      ;
; 8.589 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.857      ;
; 8.592 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.861      ;
; 8.593 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.865      ;
; 8.593 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.865      ;
; 8.593 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.865      ;
; 8.593 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.862      ;
; 8.596 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.859      ;
; 8.692 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.152     ; 2.902      ;
; 8.692 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.152     ; 2.902      ;
; 8.692 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.152     ; 2.902      ;
; 8.692 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.152     ; 2.902      ;
; 8.692 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.152     ; 2.902      ;
; 8.762 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.705      ;
; 8.785 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.693      ;
; 8.785 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.693      ;
; 8.785 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.693      ;
; 8.785 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.693      ;
; 8.785 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.693      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.546      ;
; 9.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 2.554      ;
; 9.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 2.554      ;
; 9.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 2.554      ;
; 9.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 2.554      ;
; 9.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 2.554      ;
; 9.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 2.554      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
; 9.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.148     ; 2.550      ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 48.523 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.253      ; 1.729      ;
; 97.099 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.810      ;
; 97.099 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.810      ;
; 97.099 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.810      ;
; 97.099 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.810      ;
; 97.329 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.091     ; 2.579      ;
; 97.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.546      ;
; 97.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.546      ;
; 97.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.546      ;
; 97.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.090     ; 2.546      ;
; 97.655 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.283      ;
; 97.655 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.283      ;
; 97.655 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.283      ;
; 97.655 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.283      ;
; 97.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.132      ;
; 97.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.132      ;
; 97.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.132      ;
; 97.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.132      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 97.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.945      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.007 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 1.918      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.827      ;
; 98.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.735      ;
; 98.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.735      ;
; 98.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.735      ;
; 98.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.735      ;
; 98.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.735      ;
; 98.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.735      ;
; 98.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.735      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.721      ;
; 98.218 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 1.715      ;
; 98.218 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 1.715      ;
; 98.232 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.704      ;
; 98.232 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.704      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.684      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.684      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.075     ; 1.684      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 1.691      ;
; 98.242 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.693      ;
; 98.242 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.693      ;
; 98.242 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.693      ;
; 98.665 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.272      ;
; 98.665 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.272      ;
; 98.665 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.272      ;
; 98.665 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 1.272      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.054      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.054      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.054      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.056      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.054      ;
; 63.522 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.054      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.055      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.055      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.055      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.053      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.053      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.053      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.053      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.053      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.053      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.053      ;
; 63.523 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.079     ; 3.053      ;
; 63.524 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.078     ; 3.053      ;
; 63.524 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.078     ; 3.053      ;
; 63.524 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.078     ; 3.053      ;
; 63.524 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.078     ; 3.053      ;
; 63.524 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.078     ; 3.053      ;
; 63.524 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.078     ; 3.053      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.929      ; 3.043      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.044      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.929      ; 3.043      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.929      ; 3.043      ;
; 65.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.929      ; 3.043      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.929      ; 3.042      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.931      ; 3.044      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.931      ; 3.044      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.931      ; 3.044      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.043      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.043      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.930      ; 3.043      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.931      ; 3.044      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.931      ; 3.044      ;
; 65.542 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.931      ; 3.044      ;
; 65.543 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.932      ; 3.044      ;
; 65.543 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.932      ; 3.044      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.141      ; 2.851      ;
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.141      ; 2.851      ;
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.849      ;
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.849      ;
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.849      ;
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.849      ;
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.849      ;
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.849      ;
; 0.539 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.849      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.138      ; 2.849      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.540 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.140      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 0.541 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.139      ; 2.851      ;
; 2.610 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 2.857      ;
; 2.610 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 2.857      ;
; 2.610 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 2.857      ;
; 2.610 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.611 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 2.857      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.614 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 2.862      ;
; 2.615 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 2.862      ;
; 2.615 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 2.862      ;
; 2.615 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 2.862      ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.915  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.148      ;
; 0.915  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.148      ;
; 0.915  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.148      ;
; 0.915  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.148      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.373  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.603      ;
; 1.374  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.595      ;
; 1.374  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.595      ;
; 1.374  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.050      ; 1.595      ;
; 1.376  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.610      ;
; 1.376  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.610      ;
; 1.376  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.610      ;
; 1.381  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.614      ;
; 1.381  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.614      ;
; 1.389  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.619      ;
; 1.389  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.059      ; 1.619      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.392  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.060      ; 1.623      ;
; 1.403  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.636      ;
; 1.403  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.636      ;
; 1.403  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.636      ;
; 1.403  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.636      ;
; 1.403  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.636      ;
; 1.403  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.636      ;
; 1.403  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.636      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.447  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.709      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.603  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.091      ; 1.865      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.616  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.051      ; 1.838      ;
; 1.779  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.015      ;
; 1.779  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.015      ;
; 1.779  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.015      ;
; 1.779  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.015      ;
; 1.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.081      ;
; 1.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.081      ;
; 1.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.081      ;
; 1.845  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.065      ; 2.081      ;
; 2.141  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 2.375      ;
; 2.168  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 2.403      ;
; 2.168  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 2.403      ;
; 2.168  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 2.403      ;
; 2.168  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 2.403      ;
; 2.414  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 2.649      ;
; 2.414  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 2.649      ;
; 2.414  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 2.649      ;
; 2.414  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 2.649      ;
; 51.049 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.385      ; 1.625      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                           ; To Node                                                                                                                                                                                                                ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.290 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a6 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 1.805      ;
; 1.290 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 1.805      ;
; 1.290 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 1.805      ;
; 1.290 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 1.805      ;
; 1.290 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 1.805      ;
; 1.290 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 1.805      ;
; 1.290 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.347      ; 1.805      ;
; 1.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.349      ; 1.867      ;
; 1.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.349      ; 1.867      ;
; 1.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.349      ; 1.867      ;
; 1.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.349      ; 1.867      ;
; 1.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.349      ; 1.867      ;
; 1.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.349      ; 1.867      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a15   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a14   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a13   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a12   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a11   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a10   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a9    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a8    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a7    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a6    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a5    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a4    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a3    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a2    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.798 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.360      ; 2.326      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a55  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a54  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a53  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a52  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a51  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a50  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a49  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a48  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a47  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a46  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a45  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a44  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a43  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a42  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a41  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a40  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a39  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a38  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a37  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a36  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a23  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a22  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a21  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a20  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a19  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a18  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a17  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a16  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a7   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a6   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a5   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a4   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a3   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a2   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a1   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.364      ; 2.335      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a63  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a62  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a61  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a60  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a59  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a58  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a57  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a56  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a35  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a34  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a33  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a32  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a31  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a30  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a29  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a28  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a27  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a26  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a25  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a24  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a15  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a14  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a13  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a12  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a11  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a10  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a9   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 2.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.362      ; 2.621      ;
; 3.917 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[1]                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.478      ; 4.566      ;
; 3.937 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.465      ; 4.573      ;
; 3.940 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.461      ; 4.572      ;
; 3.953 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[2]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.447      ; 4.571      ;
; 3.970 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 4.573      ;
; 3.975 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 4.572      ;
; 3.982 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 4.576      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.398      ;
; 2.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.398      ;
; 2.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.398      ;
; 2.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 2.397      ;
; 2.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 2.397      ;
; 2.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.398      ;
; 2.058 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.395      ;
; 2.058 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.395      ;
; 2.058 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.395      ;
; 2.058 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.400      ;
; 2.058 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.400      ;
; 2.058 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.400      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.413      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.413      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.396      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.413      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.413      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.059 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.405      ;
; 2.060 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.405      ;
; 2.060 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.405      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.411      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.411      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.411      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.411      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.411      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.411      ;
; 2.063 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.402      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.543      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.543      ;
; 2.298 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.543      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.544      ;
; 2.299 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.544      ;
; 2.321 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.118      ; 2.555      ;
; 2.394 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.736      ;
; 2.394 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.736      ;
; 2.394 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.736      ;
; 2.394 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.736      ;
; 2.394 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.736      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[0]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[1]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[3]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[4]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[5]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[6]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[0]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[1]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[2]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[3]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[4]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[5]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[6]       ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[7]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[2]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[3]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[4]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[6]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[5]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[7]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[8]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[9]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[0] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[1] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[2] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[3] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[4] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[5] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[6] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[7] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[8] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[9] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[2]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[7]       ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[0]              ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[1]              ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[2]              ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[3]              ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[7]              ;
; 4.243 ; 4.394        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[4]              ;
; 4.243 ; 4.394        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[5]              ;
; 4.243 ; 4.394        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[6]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[3]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[4]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[5]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[6]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[7]              ;
; 4.261 ; 4.417        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[0]              ;
; 4.261 ; 4.417        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[1]              ;
; 4.261 ; 4.417        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[2]              ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[1]       ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[4]       ;
; 4.273 ; 4.459        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[6]       ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[15]                  ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[8]                   ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[9]                   ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                         ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                           ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]                                                           ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[10]                                                          ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[4]                                                           ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[16]                                                          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                               ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                               ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                               ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                           ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]     ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                       ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                    ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[2]                               ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[11]                                                          ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                          ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[14]                                                          ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[15]                                                          ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[17]                                                          ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[3]                                                           ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[8]                                                           ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[9]                                                           ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                             ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                             ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                             ;
; 17.327 ; 17.545       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                             ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]          ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[12]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[13]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[17]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]         ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]        ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[3]         ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                               ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                               ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                               ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                               ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                              ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[1]                          ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]        ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[33]        ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]         ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[21]                                                          ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[22]                                                          ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[23]                                                          ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[29]                                                          ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[30]                                                          ;
; 17.330 ; 17.548       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]        ;
; 17.330 ; 17.548       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[44]        ;
; 17.330 ; 17.548       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                        ;
; 17.330 ; 17.548       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                  ;
; 17.330 ; 17.548       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                                  ;
; 17.330 ; 17.548       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                   ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]         ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[21]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]        ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]         ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                               ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                               ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                               ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                           ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[23]        ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[25]        ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]        ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]         ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]         ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]         ;
; 17.336 ; 17.554       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]         ;
; 17.336 ; 17.554       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]        ;
; 17.336 ; 17.554       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]        ;
; 17.336 ; 17.554       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                        ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                              ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                              ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                              ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                              ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                              ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                              ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0] ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1] ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2] ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3] ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4] ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5] ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6] ;
; 17.343 ; 17.561       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7] ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.605 ; 17.605       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.637 ; 17.637       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                       ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+
; 32.984 ; 33.202       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[0]              ;
; 32.984 ; 33.202       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[1]              ;
; 32.984 ; 33.202       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[2]              ;
; 32.984 ; 33.202       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[3]              ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp2_prev~_emulated          ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]              ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]              ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]              ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]              ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                 ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus~en                   ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus~reg0                 ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                 ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus~en                    ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus~reg0                  ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                  ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                  ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                  ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                  ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit1      ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit2      ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit3      ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit4      ;
; 33.006 ; 33.224       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit5      ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]                ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]              ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]              ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]              ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]              ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rden_sig                    ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                  ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]                 ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                 ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                 ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle           ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.end_send1      ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.end_send2      ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_released ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start    ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send1          ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send2          ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send3          ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit0      ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit6      ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit7      ;
; 33.007 ; 33.225       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_complete  ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]                ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus_buf1                 ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus_buf2                 ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid             ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[0]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[1]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[2]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[3]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[4]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[5]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[6]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[7]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[8]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[9]       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch                       ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1           ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2           ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4           ;
; 33.008 ; 33.226       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                         ;
; 33.009 ; 33.227       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated          ;
; 33.009 ; 33.227       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated          ;
; 33.009 ; 33.227       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus_buf1                  ;
; 33.009 ; 33.227       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus_buf2                  ;
; 33.009 ; 33.227       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3           ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_out[3]             ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[0]           ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[1]           ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[2]           ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[3]           ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[4]           ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[5]           ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[6]           ;
; 33.010 ; 33.228       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[7]           ;
; 33.013 ; 33.231       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[0]              ;
; 33.013 ; 33.231       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[1]              ;
; 33.013 ; 33.231       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[2]              ;
; 33.013 ; 33.231       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[3]              ;
; 33.013 ; 33.231       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[4]              ;
; 33.013 ; 33.231       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[5]              ;
; 33.013 ; 33.231       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[6]              ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.399 ; 49.632       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.399 ; 49.632       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.401 ; 49.634       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.401 ; 49.634       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.401 ; 49.634       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.403 ; 49.636       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.474 ; 49.692       ; 0.218          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ;
; 49.517 ; 49.703       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                 ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                      ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                      ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                      ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                      ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                             ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]                                                                                                                                       ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1]                                                                                                                                       ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2]                                                                                                                                       ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3]                                                                                                                                       ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                        ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                        ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                    ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                    ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                     ;
; 49.518 ; 49.704       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                     ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                    ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                          ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                          ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ;
; 49.519 ; 49.705       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.856  ; 99.856       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 99.857  ; 99.857       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.142 ; 100.142      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.143 ; 100.143      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.172 ; 100.172      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.218 ; 100.218      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.218 ; 100.218      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 100.219 ; 100.219      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 100.219 ; 100.219      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                            ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; 2.399 ; 2.570 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.381 ; 2.552 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.381 ; 2.552 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.381 ; 2.552 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.384 ; 2.555 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.393 ; 2.564 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.386 ; 2.557 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.384 ; 2.555 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.334 ; 2.504 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.392 ; 2.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.399 ; 2.570 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.395 ; 2.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.395 ; 2.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.395 ; 2.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.393 ; 2.564 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.393 ; 2.564 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.393 ; 2.564 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; 2.870 ; 3.071 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.519 ; 1.748 ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 7.245 ; 7.278 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 3.679 ; 3.993 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 1.141 ; 1.466 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.037 ; 4.337 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 2.145 ; 2.437 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.193 ; 4.484 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 2.356 ; 2.651 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; -1.561 ; -1.731 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; -1.603 ; -1.774 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; -1.603 ; -1.774 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; -1.603 ; -1.774 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; -1.606 ; -1.777 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; -1.615 ; -1.786 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; -1.608 ; -1.779 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; -1.606 ; -1.777 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; -1.561 ; -1.731 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; -1.615 ; -1.786 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; -1.622 ; -1.793 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; -1.617 ; -1.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; -1.617 ; -1.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; -1.617 ; -1.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; -1.616 ; -1.787 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; -1.616 ; -1.787 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; -1.616 ; -1.787 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; -2.025 ; -2.216 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.387  ; 1.221  ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; -0.559 ; -0.681 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; -2.975 ; -3.277 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; -0.360 ; -0.666 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -3.318 ; -3.607 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -1.336 ; -1.618 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -3.403 ; -3.657 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -1.497 ; -1.788 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 4.957  ; 5.132  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 2.750  ; 2.600  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 2.750  ; 2.600  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 2.754  ; 2.604  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 2.754  ; 2.604  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 2.742  ; 2.592  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 2.742  ; 2.592  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 2.740  ; 2.590  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 2.049  ; 1.992  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 4.957  ; 5.132  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 2.741  ; 2.591  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 2.750  ; 2.600  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 2.741  ; 2.591  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 4.968  ; 5.143  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 4.968  ; 5.143  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 2.060  ; 2.003  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 2.063  ; 2.006  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 2.753  ; 2.603  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 4.398  ; 4.731  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 3.061  ; 2.998  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 3.061  ; 2.998  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 3.061  ; 2.998  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 4.398  ; 4.731  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 4.389  ; 4.722  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.206  ; 2.169  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.930  ; 2.809  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.753  ; 2.603  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 3.049  ; 2.986  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 4.382  ; 4.715  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 3.047  ; 2.984  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 3.047  ; 2.984  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 3.047  ; 2.984  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 4.388  ; 4.721  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 3.048  ; 2.985  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 3.048  ; 2.985  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 2.742  ; 2.592  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 2.753  ; 2.603  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 2.753  ; 2.603  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 4.971  ; 5.146  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 6.852  ; 7.010  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 4.033  ; 3.897  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 3.362  ; 3.214  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 3.255  ; 3.083  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 3.201  ; 3.349  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 11.357 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 11.555 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 4.267  ; 4.535  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 2.050  ; 1.993  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 4.267  ; 4.535  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 2.049  ; 1.992  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 2.052  ; 1.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 4.269  ; 4.537  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 2.051  ; 1.994  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 2.051  ; 1.994  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 2.051  ; 1.994  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 4.269  ; 4.537  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 11.025 ; 11.750 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 5.250  ; 5.186  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 6.959  ; 6.849  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 7.817  ; 7.590  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 7.165  ; 7.294  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                            ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 1.411  ; 1.354  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 2.084  ; 1.937  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 2.084  ; 1.937  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 2.088  ; 1.941  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 2.088  ; 1.941  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 2.076  ; 1.929  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 2.076  ; 1.929  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 2.074  ; 1.927  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 1.411  ; 1.354  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 4.292  ; 4.470  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 2.075  ; 1.928  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 2.084  ; 1.937  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 2.075  ; 1.928  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 1.421  ; 1.364  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 4.302  ; 4.480  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 1.421  ; 1.364  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 1.424  ; 1.367  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 2.087  ; 1.940  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 1.567  ; 1.529  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.394  ; 2.333  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.394  ; 2.333  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.394  ; 2.333  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 3.759  ; 4.091  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 3.750  ; 4.082  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 1.567  ; 1.529  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.263  ; 2.144  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.087  ; 1.940  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.383  ; 2.322  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 3.744  ; 4.076  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.380  ; 2.319  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.380  ; 2.319  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.380  ; 2.319  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 3.750  ; 4.082  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.382  ; 2.321  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.382  ; 2.321  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 2.076  ; 1.929  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 2.087  ; 1.940  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 2.087  ; 1.940  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 4.305  ; 4.483  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 6.020  ; 6.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 3.223  ; 3.090  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 2.579  ; 2.435  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 2.477  ; 2.308  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 2.422  ; 2.567  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 10.646 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 10.846 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 1.411  ; 1.354  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 1.412  ; 1.355  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 3.629  ; 3.897  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 1.411  ; 1.354  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 3.630  ; 3.898  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 8.762  ; 9.492  ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 4.688  ; 4.627  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 6.323  ; 6.216  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 7.248  ; 7.017  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 6.519  ; 6.645  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.378 ; 3.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.378 ; 3.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.378 ; 3.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.378 ; 3.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.409 ; 5.672 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.411 ; 5.674 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.585 ; 3.475 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.595 ; 3.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.922 ; 3.794 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.647 ; 4.598 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.418 ; 6.681 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.011 ; 3.962 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.011 ; 3.962 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.011 ; 3.962 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.071 ; 6.334 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.010 ; 3.961 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.010 ; 3.961 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.353 ; 3.225 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.250 ; 5.201 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.327 ; 7.217 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.216 ; 7.479 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.116 ; 7.006 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.624 ; 2.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.624 ; 2.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.624 ; 2.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.624 ; 2.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.656 ; 4.919 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.658 ; 4.921 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.818 ; 2.708 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.827 ; 2.717 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.100 ; 2.972 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.842 ; 3.793 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.625 ; 5.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.232 ; 3.183 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.232 ; 3.183 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.232 ; 3.183 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.291 ; 5.554 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.230 ; 3.181 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.230 ; 3.181 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.554 ; 2.426 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.707 ; 4.658 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 6.696 ; 6.586 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 6.678 ; 6.941 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 6.493 ; 6.383 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.292     ; 3.341     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.292     ; 3.341     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.292     ; 3.341     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.292     ; 3.341     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.631     ; 5.368     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.639     ; 5.376     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.428     ; 3.538     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.439     ; 3.549     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.683     ; 3.811     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.513     ; 4.562     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.611     ; 6.348     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.907     ; 3.956     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.907     ; 3.956     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.907     ; 3.956     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.279     ; 6.016     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.906     ; 3.955     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.906     ; 3.955     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.156     ; 3.284     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.128     ; 5.177     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.131     ; 7.241     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.432     ; 7.169     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 6.968     ; 7.078     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.539     ; 2.588     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.539     ; 2.588     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.539     ; 2.588     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.539     ; 2.588     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.880     ; 4.617     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.887     ; 4.624     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.663     ; 2.773     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.673     ; 2.783     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.866     ; 2.994     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.711     ; 3.760     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.820     ; 5.557     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.130     ; 3.179     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.130     ; 3.179     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.130     ; 3.179     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.502     ; 5.239     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.129     ; 3.178     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.129     ; 3.178     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.360     ; 2.488     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.588     ; 4.637     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 6.504     ; 6.614     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 6.895     ; 6.632     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 6.348     ; 6.458     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                     ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.138 ; -449.056      ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.603  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 6.787  ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 29.824 ; 0.000         ;
; altera_reserved_tck                                                           ; 48.274 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.136 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.163 ; 0.000         ;
; altera_reserved_tck                                                           ; 0.186 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.188 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.194 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                  ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.132  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.905  ; 0.000         ;
; altera_reserved_tck                                                           ; 49.445 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 64.838 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.300 ; 0.000         ;
; altera_reserved_tck                                                           ; 0.491 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.690 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.142 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.187  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.655  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.369 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.601 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 33.040 ; 0.000         ;
; altera_reserved_tck                                                           ; 49.298 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.418 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                         ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                                                 ; Launch Clock                                         ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -4.138 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 3.036      ;
; -4.137 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 3.034      ;
; -3.983 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.064     ; 3.054      ;
; -3.950 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.049     ; 3.036      ;
; -3.934 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.249     ; 2.820      ;
; -3.927 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 3.022      ;
; -3.922 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.049     ; 3.008      ;
; -3.918 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.047     ; 3.006      ;
; -3.901 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.030     ; 3.006      ;
; -3.893 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.051     ; 2.977      ;
; -3.893 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.030     ; 2.998      ;
; -3.892 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.985      ;
; -3.890 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.985      ;
; -3.888 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.028     ; 2.995      ;
; -3.885 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.051     ; 2.969      ;
; -3.884 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.977      ;
; -3.861 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.066     ; 2.930      ;
; -3.853 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.066     ; 2.922      ;
; -3.845 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.047     ; 2.933      ;
; -3.821 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.719      ;
; -3.820 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.718      ;
; -3.802 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.051     ; 2.886      ;
; -3.798 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.249     ; 2.684      ;
; -3.794 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.051     ; 2.878      ;
; -3.790 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.249     ; 2.676      ;
; -3.787 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.028     ; 2.894      ;
; -3.781 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.239     ; 2.677      ;
; -3.775 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.673      ;
; -3.773 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.239     ; 2.669      ;
; -3.763 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.661      ;
; -3.761 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.239     ; 2.657      ;
; -3.759 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.854      ;
; -3.759 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.854      ;
; -3.758 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.853      ;
; -3.752 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.067     ; 2.820      ;
; -3.751 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.067     ; 2.819      ;
; -3.751 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.649      ;
; -3.747 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.230     ; 2.652      ;
; -3.744 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.227     ; 2.652      ;
; -3.744 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.067     ; 2.812      ;
; -3.743 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.067     ; 2.811      ;
; -3.739 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.230     ; 2.644      ;
; -3.734 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.632      ;
; -3.733 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.828      ;
; -3.733 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.826      ;
; -3.725 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.818      ;
; -3.716 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.047     ; 2.804      ;
; -3.710 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.239     ; 2.606      ;
; -3.708 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.043     ; 2.800      ;
; -3.708 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.047     ; 2.796      ;
; -3.705 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[2]   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.599      ;
; -3.700 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.598      ;
; -3.700 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.045     ; 2.790      ;
; -3.695 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 2.592      ;
; -3.692 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.045     ; 2.782      ;
; -3.683 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 2.580      ;
; -3.674 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.045     ; 2.764      ;
; -3.674 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[2]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.243     ; 2.566      ;
; -3.672 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 2.569      ;
; -3.671 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 2.568      ;
; -3.669 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.239     ; 2.565      ;
; -3.661 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[1]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.245     ; 2.551      ;
; -3.659 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.557      ;
; -3.653 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[1]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.245     ; 2.543      ;
; -3.651 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.047     ; 2.739      ;
; -3.648 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.743      ;
; -3.648 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.541      ;
; -3.644 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.031     ; 2.748      ;
; -3.641 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.228     ; 2.548      ;
; -3.640 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.533      ;
; -3.632 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 2.529      ;
; -3.631 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.724      ;
; -3.626 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.045     ; 2.716      ;
; -3.626 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 2.523      ;
; -3.623 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.031     ; 2.727      ;
; -3.623 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.716      ;
; -3.622 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.045     ; 2.712      ;
; -3.621 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[24] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.227     ; 2.529      ;
; -3.619 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.047     ; 2.707      ;
; -3.618 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.060     ; 2.693      ;
; -3.617 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.056     ; 2.696      ;
; -3.612 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.707      ;
; -3.611 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.250     ; 2.496      ;
; -3.611 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.706      ;
; -3.611 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.047     ; 2.699      ;
; -3.610 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.243     ; 2.502      ;
; -3.602 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.500      ;
; -3.602 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.243     ; 2.494      ;
; -3.598 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.492      ;
; -3.597 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.491      ;
; -3.594 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.687      ;
; -3.593 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.686      ;
; -3.591 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 2.488      ;
; -3.590 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.250     ; 2.475      ;
; -3.590 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.237     ; 2.488      ;
; -3.586 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.679      ;
; -3.585 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.238     ; 2.482      ;
; -3.585 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.042     ; 2.678      ;
; -3.581 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.240     ; 2.476      ;
; -3.580 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[22]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.240     ; 2.475      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 5.603 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.085     ; 5.998      ;
; 5.621 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.969      ;
; 5.652 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.085     ; 5.949      ;
; 5.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.929      ;
; 5.688 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.906      ;
; 5.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 5.883      ;
; 5.699 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 5.892      ;
; 5.701 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.889      ;
; 5.706 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.877      ;
; 5.707 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 5.867      ;
; 5.718 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.869      ;
; 5.727 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 5.864      ;
; 5.737 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.857      ;
; 5.743 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 5.837      ;
; 5.745 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 5.836      ;
; 5.754 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 5.820      ;
; 5.775 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.812      ;
; 5.783 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 5.791      ;
; 5.784 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.800      ;
; 5.786 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.797      ;
; 5.787 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.803      ;
; 5.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 5.777      ;
; 5.812 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.772      ;
; 5.813 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.086     ; 5.787      ;
; 5.817 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 5.754      ;
; 5.830 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 5.744      ;
; 5.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.753      ;
; 5.849 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.737      ;
; 5.858 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.736      ;
; 5.860 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 5.720      ;
; 5.864 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 5.707      ;
; 5.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 5.716      ;
; 5.872 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.711      ;
; 5.874 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 5.700      ;
; 5.876 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.707      ;
; 5.882 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 5.696      ;
; 5.898 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 5.695      ;
; 5.900 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 5.681      ;
; 5.903 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.683      ;
; 5.907 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.687      ;
; 5.909 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 5.665      ;
; 5.911 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.296     ; 5.479      ;
; 5.913 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 5.667      ;
; 5.918 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 5.661      ;
; 5.919 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.671      ;
; 5.929 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 5.649      ;
; 5.929 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.086     ; 5.671      ;
; 5.932 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 5.659      ;
; 5.934 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 5.645      ;
; 5.950 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 5.624      ;
; 5.954 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.630      ;
; 5.956 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.627      ;
; 5.958 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.636      ;
; 5.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.622      ;
; 5.973 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 5.607      ;
; 5.982 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.608      ;
; 5.982 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.602      ;
; 5.984 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 5.587      ;
; 5.985 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 5.589      ;
; 5.988 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 5.591      ;
; 5.996 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.303     ; 5.387      ;
; 6.004 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.579      ;
; 6.014 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 5.579      ;
; 6.017 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.567      ;
; 6.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 5.552      ;
; 6.020 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.086     ; 5.580      ;
; 6.025 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 5.547      ;
; 6.027 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 5.546      ;
; 6.029 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theWe                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.565      ;
; 6.030 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 5.550      ;
; 6.037 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.085     ; 5.564      ;
; 6.042 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.541      ;
; 6.043 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.544      ;
; 6.044 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 5.547      ;
; 6.045 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[2]                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 5.553      ;
; 6.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 5.538      ;
; 6.048 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.542      ;
; 6.049 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 5.529      ;
; 6.049 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 5.530      ;
; 6.056 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.086     ; 5.544      ;
; 6.058 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 5.523      ;
; 6.060 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.085     ; 5.541      ;
; 6.060 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.530      ;
; 6.067 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.516      ;
; 6.068 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 5.525      ;
; 6.072 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 5.500      ;
; 6.074 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 5.499      ;
; 6.075 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 5.516      ;
; 6.084 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 5.494      ;
; 6.088 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 5.491      ;
; 6.103 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.484      ;
; 6.104 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 5.475      ;
; 6.105 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.489      ;
; 6.105 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 5.488      ;
; 6.105 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 5.476      ;
; 6.110 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.476      ;
; 6.114 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theWe                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.473      ;
; 6.115 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.473      ;
; 6.115 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.472      ;
; 6.124 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 5.447      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                          ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 6.787 ; svideo_yout_dly2[6]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.918      ;
; 6.789 ; svideo_yout_dly2[5]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.913      ;
; 6.790 ; svideo_yout_dly2[5]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.915      ;
; 6.791 ; svideo_yout_dly2[6]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.911      ;
; 6.813 ; svideo_yout_dly2[5]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.889      ;
; 6.815 ; svideo_yout_dly2[6]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.887      ;
; 6.834 ; svideo_yout_dly2[6]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.870      ;
; 6.837 ; svideo_yout_dly2[5]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.867      ;
; 6.853 ; svideo_yout_dly2[6]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.851      ;
; 6.856 ; svideo_yout_dly2[5]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.848      ;
; 6.874 ; svideo_yout_dly2[5]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.830      ;
; 6.876 ; svideo_yout_dly2[6]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.828      ;
; 6.914 ; svideo_yout_dly2[7]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.788      ;
; 6.922 ; svideo_yout_dly2[7]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.783      ;
; 6.935 ; svideo_yout_dly2[4]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.767      ;
; 6.938 ; svideo_yout_dly2[7]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.764      ;
; 6.939 ; svideo_yout_dly2[4]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.766      ;
; 6.959 ; svideo_yout_dly2[4]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.743      ;
; 6.971 ; svideo_yout_dly2[7]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.733      ;
; 6.973 ; svideo_yout_dly2[6]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.731      ;
; 6.976 ; svideo_yout_dly2[5]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.728      ;
; 6.986 ; svideo_yout_dly2[4]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.718      ;
; 6.987 ; svideo_yout_dly2[7]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.717      ;
; 6.999 ; svideo_yout_dly2[7]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.705      ;
; 7.005 ; svideo_yout_dly2[4]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.699      ;
; 7.020 ; svideo_yout_dly2[4]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.684      ;
; 7.030 ; svideo_yout_dly2[2]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.672      ;
; 7.038 ; svideo_yout_dly2[2]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.667      ;
; 7.045 ; svideo_yout_dly2[3]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.660      ;
; 7.048 ; svideo_yout_dly2[3]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.654      ;
; 7.054 ; svideo_yout_dly2[2]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.648      ;
; 7.066 ; svideo_yout_dly2[1]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.639      ;
; 7.072 ; svideo_yout_dly2[3]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.630      ;
; 7.079 ; svideo_yout_dly2[6]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.625      ;
; 7.079 ; svideo_yout_dly2[1]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.623      ;
; 7.082 ; svideo_yout_dly2[5]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.622      ;
; 7.087 ; svideo_yout_dly2[2]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.617      ;
; 7.092 ; svideo_yout_dly2[3]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.612      ;
; 7.103 ; svideo_yout_dly2[2]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.601      ;
; 7.106 ; svideo_yout_dly2[1]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.596      ;
; 7.107 ; svideo_yout_dly2[7]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.597      ;
; 7.111 ; svideo_yout_dly2[3]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.593      ;
; 7.113 ; svideo_yout_dly2[1]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.591      ;
; 7.115 ; svideo_yout_dly2[2]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.589      ;
; 7.125 ; svideo_yout_dly2[4]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.579      ;
; 7.132 ; svideo_yout_dly2[1]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.572      ;
; 7.133 ; svideo_yout_dly2[3]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.571      ;
; 7.186 ; svideo_yout_dly2[1]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.518      ;
; 7.205 ; svideo_yout_dly2[0]     ; cvbs2_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.497      ;
; 7.213 ; svideo_yout_dly2[0]     ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.492      ;
; 7.213 ; svideo_yout_dly2[7]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.491      ;
; 7.223 ; svideo_yout_dly2[2]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.481      ;
; 7.229 ; svideo_yout_dly2[0]     ; cvbs2_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.047     ; 1.473      ;
; 7.231 ; svideo_yout_dly2[3]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.473      ;
; 7.231 ; svideo_yout_dly2[4]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.473      ;
; 7.252 ; svideo_yout_dly2[1]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.452      ;
; 7.262 ; svideo_yout_dly2[0]     ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.442      ;
; 7.278 ; svideo_yout_dly2[0]     ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.426      ;
; 7.290 ; svideo_yout_dly2[0]     ; cvbs2_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.414      ;
; 7.329 ; svideo_yout_dly2[2]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.375      ;
; 7.337 ; svideo_yout_dly2[3]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.367      ;
; 7.358 ; svideo_yout_dly2[1]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.346      ;
; 7.398 ; svideo_yout_dly2[0]     ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.306      ;
; 7.413 ; svideo:svideo|luma[2]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.289      ;
; 7.470 ; svideo:svideo|luma[1]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.231      ;
; 7.471 ; svideo:svideo|luma[0]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.230      ;
; 7.475 ; cvbs1_out[3]            ; cvbs2_out[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.230      ;
; 7.477 ; svideo:svideo|luma[2]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.225      ;
; 7.477 ; svideo:svideo|chroma[1] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.224      ;
; 7.481 ; svideo:svideo|luma[2]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.221      ;
; 7.481 ; svideo:svideo|chroma[1] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.220      ;
; 7.487 ; svideo:svideo|luma[4]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.215      ;
; 7.491 ; cvbs1_out[4]            ; cvbs2_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.214      ;
; 7.504 ; svideo_yout_dly2[0]     ; cvbs2_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.045     ; 1.200      ;
; 7.511 ; svideo:svideo|chroma[0] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.190      ;
; 7.512 ; svideo:svideo|chroma[3] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.189      ;
; 7.514 ; cvbs1_out[9]            ; cvbs2_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.043     ; 1.192      ;
; 7.516 ; svideo:svideo|chroma[3] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.185      ;
; 7.525 ; svideo:svideo|luma[1]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.176      ;
; 7.531 ; svideo:svideo|luma[0]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.170      ;
; 7.533 ; svideo:svideo|chroma[0] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.168      ;
; 7.538 ; svideo:svideo|luma[1]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.163      ;
; 7.539 ; svideo:svideo|luma[3]   ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.163      ;
; 7.539 ; svideo:svideo|luma[0]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.162      ;
; 7.545 ; svideo:svideo|luma[2]   ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.157      ;
; 7.545 ; svideo:svideo|chroma[1] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.156      ;
; 7.545 ; svideo:svideo|luma_2[1] ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.035     ; 1.217      ;
; 7.549 ; svideo:svideo|luma[2]   ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.153      ;
; 7.549 ; svideo:svideo|chroma[1] ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.152      ;
; 7.549 ; svideo:svideo|luma_2[1] ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.035     ; 1.213      ;
; 7.551 ; svideo:svideo|luma[4]   ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.151      ;
; 7.555 ; svideo:svideo|luma[4]   ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.095     ; 1.147      ;
; 7.567 ; svideo:svideo|chroma[2] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.134      ;
; 7.579 ; svideo:svideo|chroma[0] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.122      ;
; 7.580 ; svideo:svideo|chroma[3] ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.121      ;
; 7.582 ; svideo:svideo|chroma[2] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.119      ;
; 7.584 ; svideo:svideo|chroma[5] ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.117      ;
; 7.584 ; svideo:svideo|chroma[3] ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.117      ;
; 7.585 ; cvbs1_out[2]            ; cvbs2_out[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.044     ; 1.120      ;
; 7.588 ; svideo:svideo|chroma[5] ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.096     ; 1.113      ;
+-------+-------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                              ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                     ; To Node                                                         ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 29.824 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.470      ;
; 29.824 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.470      ;
; 29.834 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.460      ;
; 29.834 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.460      ;
; 29.853 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.442      ;
; 29.853 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.442      ;
; 29.855 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.440      ;
; 29.855 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.440      ;
; 29.949 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.345      ;
; 29.949 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.345      ;
; 29.961 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.334      ;
; 29.961 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.334      ;
; 29.966 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.377      ;
; 29.966 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.377      ;
; 30.002 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.292      ;
; 30.002 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.292      ;
; 30.009 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.285      ;
; 30.009 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.285      ;
; 30.024 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.271      ;
; 30.024 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.271      ;
; 30.054 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.289      ;
; 30.054 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.289      ;
; 30.054 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.241      ;
; 30.054 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.241      ;
; 30.084 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.210      ;
; 30.084 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.016     ; 3.210      ;
; 30.085 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.205      ;
; 30.095 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.195      ;
; 30.113 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.182      ;
; 30.113 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 3.182      ;
; 30.125 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.165      ;
; 30.135 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.155      ;
; 30.195 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.095      ;
; 30.197 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.093      ;
; 30.201 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[9]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.024      ; 3.133      ;
; 30.201 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.024      ; 3.133      ;
; 30.210 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.081      ;
; 30.210 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.080      ;
; 30.212 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.079      ;
; 30.221 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.122      ;
; 30.221 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.122      ;
; 30.226 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.065      ;
; 30.228 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.063      ;
; 30.235 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.056      ;
; 30.237 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.054      ;
; 30.238 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.053      ;
; 30.240 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.051      ;
; 30.240 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.051      ;
; 30.242 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.049      ;
; 30.242 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.049      ;
; 30.244 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.047      ;
; 30.246 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.045      ;
; 30.248 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 3.043      ;
; 30.250 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.040      ;
; 30.263 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.027      ;
; 30.270 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 3.020      ;
; 30.303 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 2.987      ;
; 30.303 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 2.987      ;
; 30.310 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.033      ;
; 30.310 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.033      ;
; 30.310 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 2.980      ;
; 30.316 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[0]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.023      ; 3.017      ;
; 30.318 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.973      ;
; 30.321 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 2.974      ;
; 30.321 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 2.974      ;
; 30.322 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.021      ;
; 30.322 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.033      ; 3.021      ;
; 30.323 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 2.972      ;
; 30.323 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.015     ; 2.972      ;
; 30.333 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.958      ;
; 30.334 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.957      ;
; 30.335 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.956      ;
; 30.335 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.956      ;
; 30.337 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.954      ;
; 30.338 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[12]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.953      ;
; 30.340 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.951      ;
; 30.340 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[12]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.951      ;
; 30.341 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.950      ;
; 30.342 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.949      ;
; 30.343 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.948      ;
; 30.343 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.948      ;
; 30.345 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 2.945      ;
; 30.346 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.945      ;
; 30.348 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.943      ;
; 30.350 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.941      ;
; 30.354 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.937      ;
; 30.366 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 2.924      ;
; 30.366 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.925      ;
; 30.372 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 2.918      ;
; 30.381 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.910      ;
; 30.382 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.909      ;
; 30.385 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3 ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 2.905      ;
; 30.391 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.900      ;
; 30.394 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.897      ;
; 30.395 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[0]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; 0.023      ; 2.938      ;
; 30.396 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.895      ;
; 30.397 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.894      ;
; 30.398 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.020     ; 2.892      ;
; 30.398 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.893      ;
; 30.402 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13]               ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.019     ; 2.889      ;
+--------+-----------------------------------------------+-----------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 48.274 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.417      ; 2.130      ;
; 48.283 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.417      ; 2.121      ;
; 48.384 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.417      ; 2.020      ;
; 48.532 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.446      ; 1.901      ;
; 48.591 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.833      ;
; 48.703 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.721      ;
; 48.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.417      ; 1.695      ;
; 48.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.677      ;
; 48.754 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.670      ;
; 48.755 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.669      ;
; 48.769 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.656      ;
; 48.773 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.651      ;
; 48.824 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 1.599      ;
; 48.854 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.570      ;
; 48.939 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 1.484      ;
; 48.946 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.479      ;
; 48.954 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.416      ; 1.449      ;
; 48.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 1.446      ;
; 49.009 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.416      ;
; 49.029 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.445      ; 1.403      ;
; 49.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.316      ;
; 49.136 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 1.287      ;
; 49.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 1.066      ;
; 49.382 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.042      ;
; 97.243 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.708      ;
; 97.243 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.708      ;
; 97.243 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.708      ;
; 97.243 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.708      ;
; 97.243 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.708      ;
; 97.513 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.437      ;
; 97.513 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.437      ;
; 97.513 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.437      ;
; 97.513 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.437      ;
; 97.513 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.437      ;
; 97.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.421      ;
; 97.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.421      ;
; 97.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.421      ;
; 97.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.421      ;
; 97.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.421      ;
; 97.596 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.355      ;
; 97.596 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.355      ;
; 97.596 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.355      ;
; 97.596 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.355      ;
; 97.596 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.355      ;
; 97.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.343      ;
; 97.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.343      ;
; 97.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.343      ;
; 97.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.343      ;
; 97.606 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.343      ;
; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 2.258      ;
; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 2.258      ;
; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 2.258      ;
; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 2.258      ;
; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 2.258      ;
; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 2.258      ;
; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 2.258      ;
; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 2.258      ;
; 97.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.269      ;
; 97.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.269      ;
; 97.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.269      ;
; 97.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.269      ;
; 97.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.269      ;
; 97.706 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 2.104      ;
; 97.711 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 2.099      ;
; 97.742 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.209      ;
; 97.742 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.209      ;
; 97.742 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.209      ;
; 97.742 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.209      ;
; 97.749 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 2.061      ;
; 97.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.181      ;
; 97.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.181      ;
; 97.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.181      ;
; 97.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.181      ;
; 97.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.181      ;
; 97.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.181      ;
; 97.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.181      ;
; 97.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.181      ;
; 97.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.179      ;
; 97.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.179      ;
; 97.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.179      ;
; 97.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.179      ;
; 97.778 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 2.032      ;
; 97.787 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.164      ;
; 97.788 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 2.022      ;
; 97.793 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 2.017      ;
; 97.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.153      ;
; 97.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.153      ;
; 97.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.153      ;
; 97.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.153      ;
; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.150      ;
; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.150      ;
; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.150      ;
; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.150      ;
; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.150      ;
; 97.802 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.046     ; 2.139      ;
; 97.811 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 1.999      ;
; 97.818 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 2.124      ;
; 97.818 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 2.124      ;
; 97.818 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 2.124      ;
; 97.841 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.108      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.136 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.463      ;
; 0.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[3]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.464      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[2]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.466      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.467      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.466      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.467      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.467      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.467      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.467      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.467      ;
; 0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.470      ;
; 0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.468      ;
; 0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.469      ;
; 0.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[5]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.469      ;
; 0.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.470      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.470      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.474      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.474      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[4]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.475      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.476      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.477      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.477      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.478      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.478      ;
; 0.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.479      ;
; 0.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.478      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[6]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.479      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep2_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.482      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep3_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.485      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep2_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.486      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[1]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_datain_reg0  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.485      ;
; 0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.488      ;
; 0.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.487      ;
; 0.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.485      ;
; 0.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.490      ;
; 0.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.484      ;
; 0.163 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.489      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|cntr_4pf:cntr1|counter_reg_bit[0]    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~portb_address_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.490      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.494      ;
; 0.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|cntr_4pf:cntr1|counter_reg_bit[0]    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_address_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.489      ;
; 0.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.492      ;
; 0.169 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.491      ;
; 0.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.500      ;
; 0.173 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.501      ;
; 0.173 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.497      ;
; 0.174 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.500      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.507      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.503      ;
; 0.180 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.506      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.502      ;
; 0.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.506      ;
; 0.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.505      ;
; 0.184 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.508      ;
; 0.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.507      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[1]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[1]                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[2]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[2]                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[3]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[3]                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|syncreset_enable_divider:enable_15_div|count_reg[0]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|syncreset_enable_divider:enable_15_div|count_reg[0]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|syncreset_enable_divider:enable_15_div|count_reg[2]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|syncreset_enable_divider:enable_15_div|count_reg[2]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|syncreset_enable_divider:enable_15_div|count_reg[3]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|syncreset_enable_divider:enable_15_div|count_reg[3]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[0]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[0]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[4]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[4]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[1]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[1]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[2]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[2]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[3]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[3]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[6]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[6]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[5]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[5]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[7]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[7]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_clock_reg                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_clock_reg                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[1]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[1]                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_reset_reg                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_reset_reg                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[2]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[2]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[0]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[0]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[1]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[1]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[3]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[3]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[4]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[4]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[6]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[6]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[5]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[5]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[7]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[7]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                           ; To Node                                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.163 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[5]                      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.824      ; 1.071      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack_end            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack_end            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1_end  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.start_get_data          ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.start_get_data          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_state         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_state         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_for_deviceconnect  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_for_deviceconnect  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[0]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[0]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[2]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[2]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[4]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[4]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[5]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[5]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[7]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[7]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_available                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_available                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.184 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte7         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte7         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte8         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte8         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte9         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte9         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte10        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte10        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte11        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte11        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait40                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait40                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_getreport_ack_end  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_getreport_ack_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait1                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait1                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter2[2]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter2[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt1_end ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt1_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait2                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait2                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait4                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait4                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter2[1]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter2[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_pktin3             ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_pktin3             ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3_end ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait6                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait6                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|set_command[1]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|set_command[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_idle            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_idle            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.start_get_data          ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.start_get_data          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait21                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait21                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.getreport_sendpkt1_end  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.getreport_sendpkt1_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait30                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait30                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte2         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte2         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte3         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte3         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte4         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte4         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte5         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte5         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte6         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte6         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.Idle                    ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.Idle                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_for_deviceconnect  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_for_deviceconnect  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_state         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_state         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_address         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_address         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|set_command[0]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|set_command[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_configuration   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_configuration   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_1ms_start     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_1ms_start     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[0]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[0]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[2]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[2]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[4]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[4]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[5]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[5]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[7]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[7]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_available                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_available                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_valid                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_valid                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_getreport_ack_end  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_getreport_ack_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait4                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait4                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[1]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_wait1     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_wait1     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_address         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_address         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_idle            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_idle            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait20                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait20                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_pktin2             ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_pktin2             ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait30                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait30                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte9         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte9         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait40                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait40                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_start     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_start     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|detach_ack                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|detach_ack                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_temp[3]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_temp[3]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid_temp                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid_temp                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt2_end ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt2_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_ack_end            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_ack_end            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait20                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait20                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|detach_ack                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|detach_ack                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|start_sendcom                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|start_sendcom                      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                             ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.315      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.318      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.318      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.319      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.319      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.319      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.320      ;
; 0.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.322      ;
; 0.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.324      ;
; 0.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.324      ;
; 0.204 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.325      ;
; 0.204 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.325      ;
; 0.205 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.326      ;
; 0.205 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.326      ;
; 0.205 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.325      ;
; 0.205 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.326      ;
; 0.205 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.326      ;
; 0.205 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.326      ;
; 0.205 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.325      ;
; 0.206 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.327      ;
; 0.206 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.327      ;
; 0.207 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.328      ;
; 0.207 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.328      ;
; 0.208 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.329      ;
; 0.208 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.329      ;
; 0.209 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.330      ;
; 0.209 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.330      ;
; 0.210 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.331      ;
; 0.213 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.333      ;
; 0.214 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.335      ;
; 0.214 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.335      ;
; 0.215 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.499      ;
; 0.216 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.178      ; 0.498      ;
; 0.219 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.178      ; 0.501      ;
; 0.221 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.178      ; 0.503      ;
; 0.223 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.507      ;
; 0.230 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.514      ;
; 0.234 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.178      ; 0.516      ;
; 0.234 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.518      ;
; 0.238 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.178      ; 0.520      ;
; 0.238 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.522      ;
; 0.246 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.530      ;
; 0.247 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.531      ;
; 0.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.373      ;
; 0.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.373      ;
; 0.253 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.374      ;
; 0.253 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.373      ;
; 0.253 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.373      ;
; 0.256 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.376      ;
; 0.257 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.378      ;
; 0.262 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.546      ;
; 0.263 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.384      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.188 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.195 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.222 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dq_oe             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.341      ;
; 0.243 ; seq_reg[0]                                                                                                      ; seq_reg[1]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.363      ;
; 0.262 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.381      ;
; 0.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.459      ;
; 0.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.459      ;
; 0.276 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.395      ;
; 0.277 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.396      ;
; 0.279 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.398      ;
; 0.284 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.403      ;
; 0.284 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.403      ;
; 0.285 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.405      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.299 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.418      ;
; 0.299 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.418      ;
; 0.301 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.304 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.423      ;
; 0.305 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.310 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.429      ;
; 0.319 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.438      ;
; 0.336 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.523      ;
; 0.342 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.529      ;
; 0.344 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.464      ;
; 0.349 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.469      ;
; 0.356 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.476      ;
; 0.366 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.559      ;
; 0.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]  ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.554      ;
; 0.371 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.558      ;
; 0.372 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.559      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.561      ;
; 0.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.567      ;
; 0.381 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.500      ;
; 0.382 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.501      ;
; 0.389 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]  ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.576      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.589      ;
; 0.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.612      ;
; 0.425 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.612      ;
; 0.426 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.545      ;
; 0.437 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.556      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.445 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.564      ;
; 0.445 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.564      ;
; 0.447 ; sdram_request_reg                                                                                               ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.567      ;
; 0.450 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.569      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.572      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.643      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.459 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.578      ;
; 0.466 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.586      ;
; 0.468 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.587      ;
; 0.478 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.597      ;
; 0.482 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.669      ;
; 0.485 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.605      ;
; 0.487 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]  ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.674      ;
; 0.488 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]  ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.675      ;
; 0.498 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]  ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.685      ;
; 0.499 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.617      ;
; 0.501 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]  ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.694      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.625      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.625      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.626      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.628      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.628      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.629      ;
; 0.512 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.630      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.637      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.638      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.639      ;
; 0.520 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.713      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.640      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.641      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.641      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                             ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                 ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.194 ; svideo:svideo|luma_acc[9] ; svideo_yout_dly1[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; svideo:svideo|luma_acc[4] ; svideo_yout_dly1[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.315      ;
; 0.197 ; svideo_yout_dly1[3]       ; svideo_yout_dly2[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.316      ;
; 0.197 ; svideo_yout_dly1[5]       ; svideo_yout_dly2[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.316      ;
; 0.199 ; svideo:svideo|luma[6]     ; svideo:svideo|luma_1[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.385      ;
; 0.241 ; svideo:svideo|luma[5]     ; svideo:svideo|luma_1[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.426      ;
; 0.242 ; svideo:svideo|luma[7]     ; svideo:svideo|luma_1[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.427      ;
; 0.242 ; svideo:svideo|luma[9]     ; svideo:svideo|luma_1[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.427      ;
; 0.261 ; svideo_yout_dly1[6]       ; svideo_yout_dly2[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.381      ;
; 0.261 ; svideo:svideo|luma_acc[3] ; svideo_yout_dly1[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.380      ;
; 0.262 ; svideo:svideo|luma_2[9]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.382      ;
; 0.263 ; svideo:svideo|luma_acc[6] ; svideo_yout_dly1[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.382      ;
; 0.265 ; svideo:svideo|luma_acc[8] ; svideo_yout_dly1[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.384      ;
; 0.266 ; svideo:svideo|luma_1[3]   ; svideo:svideo|luma_2[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.385      ;
; 0.271 ; svideo_yout_dly1[0]       ; svideo_yout_dly2[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.390      ;
; 0.272 ; svideo:svideo|luma_1[2]   ; svideo:svideo|luma_2[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.391      ;
; 0.272 ; svideo:svideo|luma_1[5]   ; svideo:svideo|luma_2[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.392      ;
; 0.275 ; svideo:svideo|luma_1[0]   ; svideo:svideo|luma_2[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.394      ;
; 0.295 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.416      ;
; 0.298 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.418      ;
; 0.300 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.420      ;
; 0.304 ; svideo:svideo|luma[6]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.490      ;
; 0.306 ; svideo:svideo|chroma[8]   ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.086      ; 0.494      ;
; 0.308 ; svideo:svideo|luma[7]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.493      ;
; 0.308 ; svideo:svideo|luma[9]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.493      ;
; 0.323 ; svideo:svideo|luma[5]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.508      ;
; 0.331 ; svideo:svideo|luma[0]     ; svideo:svideo|luma_1[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.517      ;
; 0.335 ; svideo:svideo|luma_1[9]   ; svideo:svideo|luma_2[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.455      ;
; 0.336 ; svideo:svideo|luma_1[8]   ; svideo:svideo|luma_2[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.456      ;
; 0.338 ; svideo:svideo|luma[0]     ; luma_saturated[0]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.524      ;
; 0.338 ; svideo:svideo|luma[1]     ; svideo:svideo|luma_1[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.524      ;
; 0.341 ; svideo:svideo|luma[3]     ; svideo:svideo|luma_1[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.085      ; 0.528      ;
; 0.344 ; svideo:svideo|luma[2]     ; svideo:svideo|luma_1[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.085      ; 0.531      ;
; 0.351 ; svideo:svideo|luma_1[7]   ; svideo:svideo|luma_2[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.471      ;
; 0.352 ; svideo:svideo|luma_1[6]   ; svideo:svideo|luma_2[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.471      ;
; 0.360 ; luma_saturated[3]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.479      ;
; 0.362 ; luma_saturated[2]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.481      ;
; 0.363 ; luma_saturated[6]         ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.482      ;
; 0.363 ; svideo:svideo|luma_acc[7] ; svideo_yout_dly1[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.483      ;
; 0.364 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.484      ;
; 0.366 ; svideo:svideo|luma_1[1]   ; svideo:svideo|luma_2[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.485      ;
; 0.369 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.489      ;
; 0.377 ; luma_saturated[9]         ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.496      ;
; 0.377 ; luma_saturated[4]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.496      ;
; 0.377 ; svideo_yout_dly1[4]       ; svideo_yout_dly2[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.497      ;
; 0.377 ; svideo_yout_dly1[1]       ; svideo_yout_dly2[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.497      ;
; 0.378 ; luma_saturated[5]         ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.497      ;
; 0.379 ; luma_saturated[7]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.498      ;
; 0.379 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.499      ;
; 0.380 ; svideo:svideo|luma_2[3]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.500      ;
; 0.384 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.504      ;
; 0.393 ; svideo:svideo|chroma[4]   ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.086      ; 0.581      ;
; 0.395 ; svideo:svideo|chroma[6]   ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.086      ; 0.583      ;
; 0.402 ; svideo:svideo|chroma[2]   ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.086      ; 0.590      ;
; 0.408 ; svideo:svideo|chroma[7]   ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.086      ; 0.596      ;
; 0.412 ; svideo:svideo|chroma[8]   ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.086      ; 0.600      ;
; 0.418 ; svideo:svideo|chroma[5]   ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.086      ; 0.606      ;
; 0.418 ; svideo:svideo|luma[4]     ; svideo:svideo|luma_1[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.085      ; 0.605      ;
; 0.423 ; svideo:svideo|chroma[3]   ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.086      ; 0.611      ;
; 0.423 ; svideo:svideo|luma[8]     ; svideo:svideo|luma_1[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.085      ; 0.610      ;
; 0.438 ; svideo:svideo|luma_1[4]   ; svideo:svideo|luma_2[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.557      ;
; 0.438 ; svideo:svideo|luma_acc[2] ; svideo_yout_dly1[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.558      ;
; 0.440 ; svideo_yout_dly1[7]       ; svideo_yout_dly2[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.560      ;
; 0.441 ; svideo:svideo|luma[3]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.085      ; 0.628      ;
; 0.442 ; svideo_yout_dly1[2]       ; svideo_yout_dly2[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.562      ;
; 0.444 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.564      ;
; 0.444 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.564      ;
; 0.445 ; svideo:svideo|luma_acc[5] ; svideo_yout_dly1[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.565      ;
; 0.445 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.565      ;
; 0.446 ; svideo:svideo|luma[0]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.632      ;
; 0.446 ; svideo:svideo|luma[2]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.085      ; 0.633      ;
; 0.446 ; svideo:svideo|luma[8]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.085      ; 0.633      ;
; 0.447 ; svideo:svideo|luma[4]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.085      ; 0.634      ;
; 0.452 ; svideo:svideo|luma[6]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.638      ;
; 0.452 ; svideo:svideo|luma[1]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.638      ;
; 0.453 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.573      ;
; 0.456 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.576      ;
; 0.460 ; svideo:svideo|luma_2[1]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.580      ;
; 0.467 ; svideo:svideo|luma[7]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.652      ;
; 0.469 ; luma_saturated[8]         ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.588      ;
; 0.470 ; svideo:svideo|luma[7]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.655      ;
; 0.482 ; svideo:svideo|luma[5]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.667      ;
; 0.485 ; svideo:svideo|luma[5]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.670      ;
; 0.507 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.627      ;
; 0.507 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.627      ;
; 0.508 ; luma_saturated[3]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.627      ;
; 0.508 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.628      ;
; 0.510 ; luma_saturated[1]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.629      ;
; 0.510 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.630      ;
; 0.515 ; svideo:svideo|luma[6]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.701      ;
; 0.518 ; svideo:svideo|luma[6]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.704      ;
; 0.519 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.639      ;
; 0.521 ; luma_saturated[2]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.640      ;
; 0.521 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.641      ;
; 0.522 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.642      ;
; 0.522 ; luma_saturated[6]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.641      ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                              ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 8.132 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 3.521      ;
; 8.166 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.483      ;
; 8.166 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.483      ;
; 8.166 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.483      ;
; 8.166 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.483      ;
; 8.170 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.489      ;
; 8.170 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.489      ;
; 8.170 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.489      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.351 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.299      ;
; 8.352 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.296      ;
; 8.352 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.289      ;
; 8.352 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.289      ;
; 8.352 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.296      ;
; 8.352 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.296      ;
; 8.352 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.289      ;
; 8.352 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.296      ;
; 8.352 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.296      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.297      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.298      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
; 8.353 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.301      ;
+-------+---------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                   ;
+--------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node              ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 9.905  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 1.637      ;
; 9.935  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.646      ;
; 9.935  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.646      ;
; 9.936  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.648      ;
; 9.936  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.646      ;
; 9.937  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.647      ;
; 9.937  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.646      ;
; 9.937  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.646      ;
; 9.939  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.119     ; 1.629      ;
; 9.940  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 1.622      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 1.571      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 1.564      ;
; 9.943  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.624      ;
; 9.943  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.624      ;
; 9.943  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.624      ;
; 9.945  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.566      ;
; 9.945  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.566      ;
; 9.945  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.566      ;
; 9.945  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.622      ;
; 9.945  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.622      ;
; 9.945  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.622      ;
; 9.947  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.564      ;
; 9.947  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.564      ;
; 9.947  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.564      ;
; 9.949  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.639      ;
; 9.949  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.639      ;
; 9.949  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.639      ;
; 9.949  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.639      ;
; 9.949  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.123     ; 1.615      ;
; 9.949  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.639      ;
; 9.950  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.641      ;
; 9.950  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.641      ;
; 9.950  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.640      ;
; 9.951  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 1.557      ;
; 9.952  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.620      ;
; 9.953  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.621      ;
; 9.954  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 1.562      ;
; 9.954  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.622      ;
; 9.954  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.622      ;
; 9.954  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.622      ;
; 9.954  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.620      ;
; 9.955  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.563      ;
; 9.956  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.562      ;
; 9.956  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.564      ;
; 9.956  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.564      ;
; 9.956  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.564      ;
; 9.976  ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.664      ;
; 9.976  ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.664      ;
; 9.976  ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.664      ;
; 9.976  ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.664      ;
; 9.976  ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.664      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.538      ;
; 10.060 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.530      ;
; 10.060 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.530      ;
; 10.060 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.530      ;
; 10.060 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.530      ;
; 10.060 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.530      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.472      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.472      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.472      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.472      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.472      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 1.472      ;
; 10.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.466      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
; 10.176 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 1.470      ;
+--------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 49.445 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 0.978      ;
; 98.331 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.602      ;
; 98.331 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.602      ;
; 98.331 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.602      ;
; 98.331 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.602      ;
; 98.466 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 1.465      ;
; 98.496 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.437      ;
; 98.496 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.437      ;
; 98.496 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.437      ;
; 98.496 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.054     ; 1.437      ;
; 98.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.269      ;
; 98.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.269      ;
; 98.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.269      ;
; 98.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.269      ;
; 98.768 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.182      ;
; 98.768 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.182      ;
; 98.768 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.182      ;
; 98.768 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 1.182      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.105      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.045     ; 1.073      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.034      ;
; 98.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.974      ;
; 98.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.974      ;
; 98.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.974      ;
; 98.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.974      ;
; 98.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.974      ;
; 98.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.974      ;
; 98.977 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.974      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.985 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.965      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.960      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.960      ;
; 98.992 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.958      ;
; 98.992 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.958      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.046     ; 0.947      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.046     ; 0.947      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.046     ; 0.947      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 98.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.955      ;
; 99.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.940      ;
; 99.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.940      ;
; 99.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.940      ;
; 99.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.686      ;
; 99.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.686      ;
; 99.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.686      ;
; 99.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.686      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.757      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.757      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.757      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.759      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.757      ;
; 64.838 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.757      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.047     ; 1.757      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.047     ; 1.757      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.047     ; 1.757      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.758      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.758      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.046     ; 1.758      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.047     ; 1.757      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.756      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.756      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.756      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.756      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.756      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.756      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.756      ;
; 64.839 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.048     ; 1.756      ;
; 64.840 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.047     ; 1.756      ;
; 64.840 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.047     ; 1.756      ;
; 65.972 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.079      ; 1.750      ;
; 65.972 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.079      ; 1.750      ;
; 65.972 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.079      ; 1.750      ;
; 65.972 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.079      ; 1.750      ;
; 65.972 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.079      ; 1.750      ;
; 65.972 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.079      ; 1.750      ;
; 65.972 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.079      ; 1.750      ;
; 65.972 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.079      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.973 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.080      ; 1.750      ;
; 65.974 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.081      ; 1.750      ;
; 65.974 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.081      ; 1.750      ;
; 65.974 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.081      ; 1.750      ;
; 65.974 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.081      ; 1.750      ;
; 65.974 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.081      ; 1.750      ;
; 65.974 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.081      ; 1.750      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.200      ; 1.584      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.200      ; 1.584      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.198      ; 1.582      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.300 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.583      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.198      ; 1.583      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.198      ; 1.583      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.198      ; 1.583      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.198      ; 1.583      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.199      ; 1.584      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.198      ; 1.583      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.198      ; 1.583      ;
; 0.301 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.198      ; 1.583      ;
; 1.460 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 1.589      ;
; 1.460 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 1.589      ;
; 1.460 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 1.589      ;
; 1.460 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.591      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.591      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.591      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.591      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.591      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.461 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 1.589      ;
; 1.462 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.592      ;
; 1.462 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.592      ;
; 1.462 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.592      ;
; 1.462 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.046      ; 1.592      ;
; 1.462 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 1.591      ;
; 1.462 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 1.591      ;
; 1.462 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.045      ; 1.591      ;
+-------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.491  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.612      ;
; 0.491  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.612      ;
; 0.491  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.612      ;
; 0.491  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.612      ;
; 0.711  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.832      ;
; 0.711  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.832      ;
; 0.711  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.832      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.722  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.843      ;
; 0.723  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.835      ;
; 0.723  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.835      ;
; 0.723  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.835      ;
; 0.723  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.843      ;
; 0.723  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.843      ;
; 0.727  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.848      ;
; 0.727  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.848      ;
; 0.727  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.848      ;
; 0.727  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.848      ;
; 0.727  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.848      ;
; 0.727  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.848      ;
; 0.727  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.729  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.848      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.737  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.877      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.821  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.056      ; 0.961      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.837  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.028      ; 0.949      ;
; 0.925  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.046      ;
; 0.925  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.046      ;
; 0.925  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.046      ;
; 0.925  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.046      ;
; 0.961  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.082      ;
; 0.961  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.082      ;
; 0.961  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.082      ;
; 0.961  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.082      ;
; 1.122  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 1.242      ;
; 1.130  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.251      ;
; 1.130  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.251      ;
; 1.130  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.251      ;
; 1.130  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.251      ;
; 1.249  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.370      ;
; 1.249  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.370      ;
; 1.249  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.370      ;
; 1.249  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 1.370      ;
; 50.232 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.514      ; 0.850      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                           ; To Node                                                                                                                                                                                                                ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.690 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a6 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.981      ;
; 0.690 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.981      ;
; 0.690 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.981      ;
; 0.690 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.981      ;
; 0.690 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.981      ;
; 0.690 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.981      ;
; 0.690 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.981      ;
; 0.708 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 1.003      ;
; 0.708 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 1.003      ;
; 0.708 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 1.003      ;
; 0.708 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 1.003      ;
; 0.708 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 1.003      ;
; 0.708 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 1.003      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a15   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a14   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a13   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a12   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a11   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a10   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a9    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a8    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a7    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a6    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a5    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a4    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a3    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a2    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.212      ; 1.264      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a55  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a54  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a53  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a52  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a51  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a50  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a49  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a48  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a47  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a46  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a45  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a44  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a43  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a42  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a41  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a40  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a39  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a38  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a37  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a36  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a23  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a22  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a21  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a20  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a19  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a18  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a17  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a16  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a7   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a6   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a5   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a4   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a3   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a2   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a1   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 1.269      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a63  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a62  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a61  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a60  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a59  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a58  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a57  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a56  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a35  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a34  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a33  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a32  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a31  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a30  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a29  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a28  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a27  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a26  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a25  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a24  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a15  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a14  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a13  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a12  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a11  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a10  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a9   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.425      ;
; 2.239 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[1]                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.564      ;
; 2.244 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.241      ; 2.569      ;
; 2.245 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.239      ; 2.568      ;
; 2.254 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[2]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 2.567      ;
; 2.258 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.227      ; 2.569      ;
; 2.261 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 2.568      ;
; 2.263 ; sdram_reset_n_reg                                                                                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 2.570      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 1.339      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.338      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.338      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.342      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.342      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.342      ;
; 1.142 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.097      ; 1.342      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.335      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.335      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.335      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.335      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.335      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.335      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.335      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.333      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.333      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.333      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.332      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.332      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.334      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.093      ; 1.339      ;
; 1.143 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.333      ;
; 1.147 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.340      ;
; 1.147 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.340      ;
; 1.147 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.340      ;
; 1.147 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.340      ;
; 1.147 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.340      ;
; 1.147 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.340      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.148 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.335      ;
; 1.260 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.409      ;
; 1.260 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.409      ;
; 1.260 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.409      ;
; 1.261 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.410      ;
; 1.261 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.410      ;
; 1.273 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.068      ; 1.416      ;
; 1.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.509      ;
; 1.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.509      ;
; 1.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.509      ;
; 1.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.509      ;
; 1.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.509      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[2]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[3]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[4]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[6]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[0]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[1]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[3]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[4]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[5]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[6]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[0]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[1]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[2]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[3]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[4]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[5]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[6]       ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[7]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[5]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[7]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[8]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[9]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[0] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[1] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[2] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[3] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[4] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[5] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[6] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[7] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[8] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[9] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[2]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[7]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[2]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[3]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[4]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[6]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[0]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[1]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[3]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[4]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[5]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[6]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[0]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[1]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[2]       ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[3]       ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[15]                  ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                          ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                       ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_address_reg0    ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|sin_cos:tab_inst|sin_rom:sin_inst|altsyncram:altsyncram_component|altsyncram_r842:auto_generated|ram_block1a0~porta_address_reg0                                                                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|sin_cos:tab_inst|sin_rom:sin_inst|altsyncram:altsyncram_component|altsyncram_r842:auto_generated|ram_block1a3~porta_address_reg0                                                                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_address_reg0    ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a10                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a11                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a12                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a13                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a14                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a15                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a24                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a25                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a26                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a27                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a28                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a29                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a30                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a31                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a32                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a33                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a34                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a35                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a56                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a57                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a58                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a59                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a60                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a61                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a62                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a63                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~portb_address_reg0    ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a9                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_address_reg0     ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|sin_cos:tab_inst|sin_rom:sin_inst|altsyncram:altsyncram_component|altsyncram_r842:auto_generated|ram_block1a0~portb_address_reg0                                                                                             ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|sin_cos:tab_inst|sin_rom:sin_inst|altsyncram:altsyncram_component|altsyncram_r842:auto_generated|ram_block1a3~portb_address_reg0                                                                                             ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a1                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a2                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a3                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a4                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a5                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a6                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a1                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a2                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a3                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a4                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a5                     ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0                       ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~portb_address_reg0    ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a1                       ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a16                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a17                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a18                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a19                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a2                       ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a20                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a21                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a22                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a23                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a3                       ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a36                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a37                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a38                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a39                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a4                       ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a40                      ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a41                      ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.615 ; 17.615       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.626 ; 17.626       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 33.040 ; 33.270       ; 0.230          ; Low Pulse Width  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~porta_address_reg0 ;
; 33.040 ; 33.270       ; 0.230          ; Low Pulse Width  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~porta_re_reg       ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[1]                                                                                                                                 ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[2]                                                                                                                                 ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[4]                                                                                                                                 ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[6]                                                                                                                                 ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[7]                                                                                                                                 ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[0]                                                                                                                                      ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[1]                                                                                                                                      ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[2]                                                                                                                                      ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[3]                                                                                                                                      ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[4]                                                                                                                                      ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[5]                                                                                                                                      ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[6]                                                                                                                                      ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[7]                                                                                                                                      ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                                                                                                                                    ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack                                                                                                                              ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_getreport_ack                                                                                                                    ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1                                                                                                                   ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2                                                                                                                   ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                                                                                                                                 ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                                                                                                                                 ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait30                                                                                                                                ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait40                                                                                                                                ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                                                                                                                                 ;
; 33.062 ; 33.278       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_ack2                                                                                                                             ;
; 33.063 ; 33.279       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[0]                                                                                                                                 ;
; 33.063 ; 33.279       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[5]                                                                                                                                 ;
; 33.063 ; 33.279       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1_end                                                                                                                ;
; 33.063 ; 33.279       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack_end                                                                                                                          ;
; 33.063 ; 33.279       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end                                                                                                               ;
; 33.063 ; 33.279       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end                                                                                                               ;
; 33.063 ; 33.279       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end                                                                                                               ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[10]                                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[11]                                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[12]                                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[13]                                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[14]                                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[1]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[2]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[3]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[4]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[5]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[6]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[7]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[8]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[9]                                                                                                                                  ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[0]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[1]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[2]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[3]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[0]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[1]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[2]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[3]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[4]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[5]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[6]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[7]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[8]                                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[0]                                                                                                                                    ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[1]                                                                                                                                    ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[2]                                                                                                                                    ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[3]                                                                                                                                    ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[4]                                                                                                                                    ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[5]                                                                                                                                    ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[6]                                                                                                                                    ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[7]                                                                                                                                    ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_temp[3]                                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_reset[0]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_reset[1]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_reset[2]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_reset[3]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_reset[4]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_reset[5]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_reset[6]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_reset[7]                                                                                                                                      ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.crc_complete                                                                                                                          ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_address                                                                                                                       ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte3                                                                                                                            ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte4                                                                                                                            ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte5                                                                                                                            ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte6                                                                                                                            ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte7                                                                                                                            ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte8                                                                                                                            ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte9                                                                                                                            ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_pktin2                                                                                                                           ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_pktin3                                                                                                                           ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_pktin4                                                                                                                           ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_getreport_ack_end                                                                                                                ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_manage2                                                                                                                           ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_release                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_start                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_wait1                                                                                                                   ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait20                                                                                                                                ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait21                                                                                                                                ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait4                                                                                                                                 ;
; 33.064 ; 33.280       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_pktin1                                                                                                                           ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.298 ; 49.528       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.298 ; 49.528       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.299 ; 49.529       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.299 ; 49.529       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.300 ; 49.530       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.301 ; 49.531       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.314 ; 49.530       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                 ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                             ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                          ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]                                                                                                                                       ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1]                                                                                                                                       ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2]                                                                                                                                       ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3]                                                                                                                                       ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                       ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                        ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                        ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg                                                                                                                                           ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                     ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                      ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                     ;
; 49.357 ; 49.541       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                     ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.358 ; 49.542       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 99.449  ; 99.449       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.460  ; 99.460       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.462  ; 99.462       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.538 ; 100.538      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.539 ; 100.539      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.551 ; 100.551      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.579 ; 100.579      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 100.579 ; 100.579      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 100.580 ; 100.580      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.580 ; 100.580      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                            ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; 1.419 ; 1.970 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 1.405 ; 1.956 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 1.405 ; 1.956 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 1.405 ; 1.956 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 1.407 ; 1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 1.417 ; 1.968 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 1.409 ; 1.960 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 1.407 ; 1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 1.385 ; 1.934 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 1.413 ; 1.964 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 1.419 ; 1.970 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; 1.755 ; 2.265 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 0.418 ; 0.822 ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 2.814 ; 3.471 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 2.197 ; 2.949 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 0.781 ; 1.529 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 2.361 ; 3.147 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 1.303 ; 2.098 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 2.416 ; 3.220 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 1.322 ; 2.142 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; -0.937 ; -1.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; -0.968 ; -1.519 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; -0.960 ; -1.511 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; -0.937 ; -1.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; -0.964 ; -1.515 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; -0.970 ; -1.521 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; -1.262 ; -1.768 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.146  ; 0.644  ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 0.329  ; -0.155 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; -1.786 ; -2.532 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; -0.329 ; -1.064 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -1.942 ; -2.721 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.835 ; -1.622 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -1.959 ; -2.741 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.830 ; -1.637 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 3.442  ; 3.819  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 1.672  ; 1.577  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 1.672  ; 1.577  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 1.675  ; 1.580  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 1.675  ; 1.580  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 1.668  ; 1.573  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 1.668  ; 1.573  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 1.666  ; 1.571  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 1.228  ; 1.202  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 3.442  ; 3.819  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 1.667  ; 1.572  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 1.672  ; 1.577  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 1.667  ; 1.572  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 3.449  ; 3.826  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 3.449  ; 3.826  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 1.235  ; 1.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 1.237  ; 1.211  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 1.674  ; 1.579  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 3.089  ; 3.564  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 1.918  ; 1.876  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 1.918  ; 1.876  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 1.918  ; 1.876  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 3.089  ; 3.564  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 3.079  ; 3.554  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 1.311  ; 1.372  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 1.771  ; 1.767  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 1.674  ; 1.579  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 1.910  ; 1.868  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 3.077  ; 3.552  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 1.909  ; 1.867  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 1.909  ; 1.867  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 1.909  ; 1.867  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 3.082  ; 3.557  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 1.909  ; 1.867  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 1.909  ; 1.867  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 1.668  ; 1.573  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 1.674  ; 1.579  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 1.674  ; 1.579  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 3.451  ; 3.828  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 4.334  ; 4.966  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 2.228  ; 2.344  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 1.864  ; 1.910  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 1.777  ; 1.814  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 1.902  ; 1.858  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 10.169 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 10.643 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 3.005  ; 3.451  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 1.230  ; 1.204  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 3.005  ; 3.451  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 1.228  ; 1.202  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 1.231  ; 1.205  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 3.007  ; 3.453  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 1.230  ; 1.204  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 1.230  ; 1.204  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 1.230  ; 1.204  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 3.007  ; 3.453  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 6.316  ; 7.111  ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 3.024  ; 3.148  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 3.901  ; 4.047  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 5.395  ; 4.805  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 4.251  ; 4.085  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                           ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 1.273 ; 1.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 1.273 ; 1.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 1.264 ; 1.172  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 3.040 ; 3.420  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 1.265 ; 1.173  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 1.265 ; 1.173  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 0.851 ; 0.825  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 3.047 ; 3.427  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 0.851 ; 0.825  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 0.853 ; 0.827  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 0.927 ; 0.989  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.705 ; 3.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.695 ; 3.171  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 0.927 ; 0.989  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 1.369 ; 1.369  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 1.508 ; 1.470  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.693 ; 3.169  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.698 ; 3.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 3.049 ; 3.429  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 3.853 ; 4.477  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 1.760 ; 1.870  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 1.410 ; 1.453  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 1.328 ; 1.362  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 1.445 ; 1.404  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 9.754 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;       ; 10.226 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 2.621 ; 3.067  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 0.847 ; 0.821  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 2.623 ; 3.069  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 5.148 ; 5.943  ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 2.706 ; 2.826  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 3.542 ; 3.685  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 5.067 ; 4.481  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 3.880 ; 3.718  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.969 ; 1.968 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.969 ; 1.968 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.969 ; 1.968 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.969 ; 1.968 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.578 ; 4.025 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.586 ; 4.033 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.013 ; 2.046 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.016 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.165 ; 2.110 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.667 ; 2.666 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.137 ; 4.584 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.321 ; 2.320 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.321 ; 2.320 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.321 ; 2.320 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.951 ; 4.398 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.320 ; 2.319 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.320 ; 2.319 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.876 ; 1.821 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.057 ; 3.056 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 4.123 ; 4.156 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 4.617 ; 5.064 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 4.033 ; 4.066 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.527 ; 1.526 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.527 ; 1.526 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.527 ; 1.526 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.527 ; 1.526 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.137 ; 3.584 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.145 ; 3.592 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.563 ; 1.596 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.566 ; 1.599 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.699 ; 1.644 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.197 ; 2.196 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.674 ; 4.121 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.865 ; 1.864 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.865 ; 1.864 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.865 ; 1.864 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.495 ; 3.942 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.864 ; 1.863 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.864 ; 1.863 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.420 ; 1.365 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.743 ; 2.742 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 3.760 ; 3.793 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 4.305 ; 4.752 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 3.673 ; 3.706 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.042     ; 2.043     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.042     ; 2.043     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.042     ; 2.043     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.042     ; 2.043     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.093     ; 3.646     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.105     ; 3.658     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.141     ; 2.108     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.149     ; 2.116     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.221     ; 2.276     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.827     ; 2.828     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.730     ; 4.283     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.438     ; 2.439     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.438     ; 2.439     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.438     ; 2.439     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.516     ; 4.069     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.437     ; 2.438     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.437     ; 2.438     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.895     ; 1.950     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.144     ; 3.145     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 4.260     ; 4.227     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 5.163     ; 4.716     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 4.165     ; 4.132     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.597     ; 1.598     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.597     ; 1.598     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.597     ; 1.598     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.597     ; 1.598     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.649     ; 3.202     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.661     ; 3.214     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.688     ; 1.655     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.696     ; 1.663     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.751     ; 1.806     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.350     ; 2.351     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.260     ; 3.813     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.978     ; 1.979     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.978     ; 1.979     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.978     ; 1.979     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.055     ; 3.608     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.977     ; 1.978     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.977     ; 1.978     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.436     ; 1.491     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.826     ; 2.827     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 3.892     ; 3.859     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 4.848     ; 4.401     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 3.801     ; 3.768     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                          ;
+--------------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+
; Clock                                                                          ; Setup    ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+
; Worst-case Slack                                                               ; -8.386   ; 0.136 ; 4.736    ; 0.300   ; 4.129               ;
;  FPGA_CLK                                                                      ; N/A      ; N/A   ; N/A      ; N/A     ; 99.418              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.177   ; 0.188 ; 8.119    ; 1.142   ; 5.595               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -8.386   ; 0.136 ; 4.736    ; 0.690   ; 17.322              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.608    ; 0.194 ; N/A      ; N/A     ; 4.129               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A   ; N/A      ; N/A     ; 17.589              ;
;  altera_reserved_tck                                                           ; 45.858   ; 0.186 ; 48.258   ; 0.491   ; 49.298              ;
;  mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 26.068   ; 0.163 ; 63.187   ; 0.300   ; 32.984              ;
; Design-wide TNS                                                                ; -917.745 ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  FPGA_CLK                                                                      ; N/A      ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.533   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -917.212 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000    ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  altera_reserved_tck                                                           ; 0.000    ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.000    ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+--------------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                            ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; 2.724 ; 2.903 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.708 ; 2.887 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.717 ; 2.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.709 ; 2.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.708 ; 2.887 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.656 ; 2.834 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.717 ; 2.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.724 ; 2.903 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.718 ; 2.897 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.718 ; 2.897 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.718 ; 2.897 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; 3.255 ; 3.450 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.519 ; 1.748 ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 7.323 ; 7.455 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 4.216 ; 4.618 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 1.414 ; 1.833 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.594 ; 5.018 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 2.497 ; 2.903 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.752 ; 5.186 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 2.675 ; 3.105 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; -0.937 ; -1.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; -0.968 ; -1.519 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; -0.960 ; -1.511 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; -0.937 ; -1.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; -0.964 ; -1.515 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; -0.970 ; -1.521 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; -1.262 ; -1.768 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.667  ; 1.515  ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 0.329  ; -0.155 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; -1.786 ; -2.532 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; -0.329 ; -0.666 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -1.942 ; -2.721 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.835 ; -1.618 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -1.959 ; -2.741 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.830 ; -1.637 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 5.688  ; 5.935  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 3.087  ; 2.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 3.087  ; 2.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 3.072  ; 2.859  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 2.251  ; 2.177  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 5.688  ; 5.935  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 3.073  ; 2.860  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 3.073  ; 2.860  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 5.701  ; 5.948  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 5.701  ; 5.948  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 2.264  ; 2.190  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 2.265  ; 2.191  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 3.085  ; 2.872  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 5.024  ; 5.448  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 5.024  ; 5.448  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 5.015  ; 5.439  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.410  ; 2.389  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 3.272  ; 3.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 3.086  ; 2.873  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 3.443  ; 3.298  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 5.008  ; 5.432  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 5.014  ; 5.438  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 3.442  ; 3.297  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 3.442  ; 3.297  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 3.086  ; 2.873  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 3.085  ; 2.872  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 5.703  ; 5.950  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 7.607  ; 7.993  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 4.347  ; 4.288  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 3.620  ; 3.528  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 3.505  ; 3.388  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 3.510  ; 3.604  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 11.898 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 12.246 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 4.868  ; 5.254  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 2.252  ; 2.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 4.868  ; 5.254  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 2.251  ; 2.177  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 2.254  ; 2.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 4.870  ; 5.256  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 4.870  ; 5.256  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 11.789 ; 12.749 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 5.760  ; 5.734  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 7.620  ; 7.614  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 8.887  ; 8.489  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 7.951  ; 7.983  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                           ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 1.273 ; 1.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 1.273 ; 1.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 1.264 ; 1.172  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 3.040 ; 3.420  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 1.265 ; 1.173  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 1.265 ; 1.173  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 0.851 ; 0.825  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 3.047 ; 3.427  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 0.851 ; 0.825  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 0.853 ; 0.827  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 0.927 ; 0.989  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.705 ; 3.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.695 ; 3.171  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 0.927 ; 0.989  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 1.369 ; 1.369  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 1.508 ; 1.470  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.693 ; 3.169  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.698 ; 3.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 3.049 ; 3.429  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 3.853 ; 4.477  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 1.760 ; 1.870  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 1.410 ; 1.453  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 1.328 ; 1.362  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 1.445 ; 1.404  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 9.754 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;       ; 10.226 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 2.621 ; 3.067  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 0.847 ; 0.821  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 2.623 ; 3.069  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 5.148 ; 5.943  ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 2.706 ; 2.826  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 3.542 ; 3.685  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 5.067 ; 4.481  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 3.880 ; 3.718  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin                 ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_B[0]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH_n        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML_n        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CLK             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CS_n            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_DOUT            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus1              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus1             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus2              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus2             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; altera_reserved_tdo ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------------+
; Input Transition Times                                                 ;
+---------------------+--------------+-----------------+-----------------+
; Pin                 ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------------+--------------+-----------------+-----------------+
; CFG_DIN             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus1              ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus1             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus2              ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus2             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK            ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tms ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tck ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tdi ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+---------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_BA[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CS_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_RAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_WE_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQML_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CLK           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CLK              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CMD              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_DAT3             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; CFG_CLK             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.15e-09 V                   ; 3.18 V              ; -0.0303 V           ; 0.317 V                              ; 0.07 V                               ; 3.25e-10 s                  ; 3.88e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.15e-09 V                  ; 3.18 V             ; -0.0303 V          ; 0.317 V                             ; 0.07 V                              ; 3.25e-10 s                 ; 3.88e-10 s                 ; No                        ; Yes                       ;
; CFG_CS_n            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; CFG_DOUT            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; dplus1              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; dminus1             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; dplus2              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; dminus2             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; altera_reserved_tdo ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.09e-08 V                   ; 3.11 V              ; 5.09e-08 V          ; 0.193 V                              ; 0.27 V                               ; 1.07e-09 s                  ; 2.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.09e-08 V                  ; 3.11 V             ; 5.09e-08 V         ; 0.193 V                             ; 0.27 V                              ; 1.07e-09 s                 ; 2.77e-09 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CS_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_WE_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQML_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CLK              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CMD              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_DAT3             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CLK             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.52e-07 V                   ; 3.14 V              ; -0.0428 V           ; 0.161 V                              ; 0.071 V                              ; 4.71e-10 s                  ; 4.5e-10 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 6.52e-07 V                  ; 3.14 V             ; -0.0428 V          ; 0.161 V                             ; 0.071 V                             ; 4.71e-10 s                 ; 4.5e-10 s                  ; Yes                       ; Yes                       ;
; CFG_CS_n            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; CFG_DOUT            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; dplus1              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; dminus1             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; dplus2              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; dminus2             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; altera_reserved_tdo ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.8e-06 V                    ; 3.09 V              ; 5.8e-06 V           ; 0.119 V                              ; 0.138 V                              ; 1.28e-09 s                  ; 3.52e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.8e-06 V                   ; 3.09 V             ; 5.8e-06 V          ; 0.119 V                             ; 0.138 V                             ; 1.28e-09 s                 ; 3.52e-09 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; VGA_B[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_L             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_R             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_BA[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_BA[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_RAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_DQMH_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQML_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CLK           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_CKE           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_A[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CLK              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_DAT3             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; CFG_CLK             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.59e-08 V                   ; 3.58 V              ; -0.0703 V           ; 0.234 V                              ; 0.091 V                              ; 2.93e-10 s                  ; 3.09e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.59e-08 V                  ; 3.58 V             ; -0.0703 V          ; 0.234 V                             ; 0.091 V                             ; 2.93e-10 s                 ; 3.09e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CS_n            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; CFG_DOUT            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; dplus1              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; dminus1             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; dplus2              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; dminus2             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; altera_reserved_tdo ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.7e-07 V                    ; 3.51 V              ; -0.00915 V          ; 0.24 V                               ; 0.283 V                              ; 8.77e-10 s                  ; 2.48e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 5.7e-07 V                   ; 3.51 V             ; -0.00915 V         ; 0.24 V                              ; 0.283 V                             ; 8.77e-10 s                 ; 2.48e-09 s                 ; No                        ; No                        ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1847     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 124698   ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6423     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 22392735 ; 0        ; 0        ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 800      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 117      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 224      ; 0        ; 0        ; 0        ;
; altera_reserved_tck                                                           ; altera_reserved_tck                                                           ; 1909     ; 0        ; 35       ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 3366     ; 140      ; 1681     ; 10371    ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1847     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 124698   ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6423     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 22392735 ; 0        ; 0        ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 800      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 117      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 224      ; 0        ; 0        ; 0        ;
; altera_reserved_tck                                                           ; altera_reserved_tck                                                           ; 1909     ; 0        ; 35       ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 3366     ; 140      ; 1681     ; 10371    ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1743     ; 0        ; 0        ; 0        ;
; altera_reserved_tck                                                           ; altera_reserved_tck                                                           ; 88       ; 0        ; 1        ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 62       ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1743     ; 0        ; 0        ; 0        ;
; altera_reserved_tck                                                           ; altera_reserved_tck                                                           ; 88       ; 0        ; 1        ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 62       ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 3     ; 3    ;
; Unconstrained Input Ports       ; 23    ; 23   ;
; Unconstrained Input Port Paths  ; 88    ; 88   ;
; Unconstrained Output Ports      ; 55    ; 55   ;
; Unconstrained Output Port Paths ; 76    ; 76   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Mon Nov  3 22:22:48 2014
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Warning (335093): TimeQuest Timing Analyzer is analyzing 6 combinational loops as latches.
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity sld_jtag_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz   
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 225.00 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]}
    Info (332110): create_generated_clock -source {mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {mcc_pll3|altpll_component|auto_generated|pll1|clk[0]} {mcc_pll3|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332060): Node: USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: reset_usbdrv was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -8.386
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -8.386      -917.212 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.177        -0.533 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.608         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    26.068         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    45.858         0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.339
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.339         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.412         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.413         0.000 altera_reserved_tck 
    Info (332119):     0.413         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.440         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info (332146): Worst-case recovery slack is 4.736
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.736         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.119         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    48.258         0.000 altera_reserved_tck 
    Info (332119):    63.187         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 0.633
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.633         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.012         0.000 altera_reserved_tck 
    Info (332119):     1.422         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.292         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.130
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.130         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     5.595         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.336         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.594         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    33.035         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    49.485         0.000 altera_reserved_tck 
    Info (332119):    99.796         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: reset_usbdrv was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -7.623
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.623      -828.251 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.779         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.972         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    26.675         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    46.366         0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.345
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.345         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.362         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.363         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.363         0.000 altera_reserved_tck 
    Info (332119):     0.406         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info (332146): Worst-case recovery slack is 5.370
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.370         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.482         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    48.523         0.000 altera_reserved_tck 
    Info (332119):    63.522         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 0.539
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.539         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.915         0.000 altera_reserved_tck 
    Info (332119):     1.290         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.057         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.129
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.129         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     5.596         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.322         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.589         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    32.984         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    49.399         0.000 altera_reserved_tck 
    Info (332119):    99.778         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: reset_usbdrv was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.138
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -4.138      -449.056 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     5.603         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     6.787         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    29.824         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    48.274         0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.136
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.136         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.163         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.186         0.000 altera_reserved_tck 
    Info (332119):     0.188         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.194         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info (332146): Worst-case recovery slack is 8.132
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     8.132         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.905         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    49.445         0.000 altera_reserved_tck 
    Info (332119):    64.838         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 0.300
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.300         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.491         0.000 altera_reserved_tck 
    Info (332119):     0.690         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.142         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.187
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.187         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     5.655         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.369         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.601         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    33.040         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    49.298         0.000 altera_reserved_tck 
    Info (332119):    99.418         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 13 warnings
    Info: Peak virtual memory: 522 megabytes
    Info: Processing ended: Mon Nov  3 22:23:37 2014
    Info: Elapsed time: 00:00:49
    Info: Total CPU time (on all processors): 00:00:35


