TimeQuest Timing Analyzer report for atari800core
Sat Jan 16 03:52:55 2016
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
 15. Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 18. Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 19. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 20. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 21. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
 23. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 24. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 25. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 26. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 27. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 28. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 29. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 30. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 35. Setup Times
 36. Hold Times
 37. Clock to Output Times
 38. Minimum Clock to Output Times
 39. Output Enable Times
 40. Minimum Output Enable Times
 41. Output Disable Times
 42. Minimum Output Disable Times
 43. Slow 1200mV 85C Model Metastability Report
 44. Slow 1200mV 0C Model Fmax Summary
 45. Slow 1200mV 0C Model Setup Summary
 46. Slow 1200mV 0C Model Hold Summary
 47. Slow 1200mV 0C Model Recovery Summary
 48. Slow 1200mV 0C Model Removal Summary
 49. Slow 1200mV 0C Model Minimum Pulse Width Summary
 50. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 51. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
 52. Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 53. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 54. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 55. Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 56. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 57. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 58. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 59. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
 60. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 61. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 63. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 65. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 66. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 68. Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 69. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 70. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 71. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 72. Setup Times
 73. Hold Times
 74. Clock to Output Times
 75. Minimum Clock to Output Times
 76. Output Enable Times
 77. Minimum Output Enable Times
 78. Output Disable Times
 79. Minimum Output Disable Times
 80. Slow 1200mV 0C Model Metastability Report
 81. Fast 1200mV 0C Model Setup Summary
 82. Fast 1200mV 0C Model Hold Summary
 83. Fast 1200mV 0C Model Recovery Summary
 84. Fast 1200mV 0C Model Removal Summary
 85. Fast 1200mV 0C Model Minimum Pulse Width Summary
 86. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 87. Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 88. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
 89. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 90. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 91. Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 92. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 93. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 94. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 95. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
 96. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 97. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 98. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 99. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
100. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
101. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
102. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
103. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
104. Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
106. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
108. Setup Times
109. Hold Times
110. Clock to Output Times
111. Minimum Clock to Output Times
112. Output Enable Times
113. Minimum Output Enable Times
114. Output Disable Times
115. Minimum Output Disable Times
116. Fast 1200mV 0C Model Metastability Report
117. Multicorner Timing Analysis Summary
118. Setup Times
119. Hold Times
120. Clock to Output Times
121. Minimum Clock to Output Times
122. Board Trace Model Assignments
123. Input Transition Times
124. Slow Corner Signal Integrity Metrics
125. Fast Corner Signal Integrity Metrics
126. Setup Transfers
127. Hold Transfers
128. Recovery Transfers
129. Removal Transfers
130. Report TCCS
131. Report RSKM
132. Unconstrained Paths
133. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.27        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  26.7%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sat Jan 16 03:52:41 2016 ;
+------------------+--------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+
; Clock Name                                                                     ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                        ; Source                                                                           ; Targets                                                                            ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.640  ; 85.91 MHz ; 0.000 ; 5.820   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 34.920  ; 28.64 MHz ; 0.000 ; 17.460  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.640  ; 85.91 MHz ; 7.638 ; 13.458  ; 50.00      ; 1         ; 3           ; 236.2 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.460  ; 57.27 MHz ; 0.000 ; 8.730   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 34.920  ; 28.64 MHz ; 0.000 ; 17.460  ; 50.00      ; 11        ; 63          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                       ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                               ;                                                                                  ; { FPGA_CLK }                                                                       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; Generated ; 20.833  ; 48.0 MHz  ; 0.000 ; 10.416  ; 50.00      ; 5         ; 48          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                      ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                            ; { usb_pll|altpll_component|auto_generated|pll1|clk[0] }                            ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                             ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                     ; Note                                           ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
; 34.12 MHz  ; 34.12 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 92.63 MHz  ; 40.0 MHz        ; FPGA_CLK                                                                       ; limit due to minimum period restriction (tmin) ;
; 120.9 MHz  ; 120.9 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;                                                ;
; 123.35 MHz ; 123.35 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 141.4 MHz  ; 141.4 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                     ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.539 ; -134.978      ;
; FPGA_CLK                                                                       ; -0.215 ; -0.215        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; -0.190 ; -1.873        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.070  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 9.353  ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                      ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; -1.918 ; -73.383       ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.453  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.454  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.455  ; 0.000         ;
; FPGA_CLK                                                                       ; 0.494  ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                  ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.996  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.513  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 11.686 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                  ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.740 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.313 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.770 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                       ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.518  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.431  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10.108 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.028 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.423 ; 0.000         ;
; FPGA_CLK                                                                       ; 89.439 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; -3.539 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.537     ; 1.046      ;
; -3.529 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.537     ; 1.036      ;
; -3.343 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.113     ; 1.274      ;
; -3.325 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.299      ;
; -3.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.113     ; 1.118      ;
; -3.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.113     ; 1.100      ;
; -3.163 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.114     ; 1.093      ;
; -3.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.114     ; 1.091      ;
; -3.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.132      ;
; -3.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.132      ;
; -3.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.130      ;
; -3.152 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.126      ;
; -3.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.099      ;
; -3.123 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.097      ;
; -3.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.095      ;
; -3.120 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.094      ;
; -3.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 1.090      ;
; -3.092 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.063     ; 1.073      ;
; -3.085 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.063     ; 1.066      ;
; -3.070 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.063     ; 1.051      ;
; -3.054 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.063     ; 1.035      ;
; -3.051 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.063     ; 1.032      ;
; -3.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.114     ; 0.934      ;
; -2.986 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.122     ; 0.908      ;
; -2.979 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.114     ; 0.909      ;
; -2.979 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.115     ; 0.908      ;
; -2.978 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.114     ; 0.908      ;
; -2.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.114     ; 0.907      ;
; -2.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.114     ; 0.907      ;
; -2.971 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.107     ; 0.908      ;
; -2.969 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.107     ; 0.906      ;
; -2.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.113     ; 0.881      ;
; -2.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.113     ; 0.881      ;
; -2.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.107     ; 0.882      ;
; -2.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.076     ; 0.910      ;
; -2.936 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 0.910      ;
; -2.935 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 0.909      ;
; -2.935 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 0.909      ;
; -2.933 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 0.907      ;
; -2.933 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 0.907      ;
; -2.932 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.070     ; 0.906      ;
; -2.929 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.063     ; 0.910      ;
; -2.928 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.063     ; 0.909      ;
; -2.913 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.077     ; 0.880      ;
; 2.424  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[6]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.155     ; 9.062      ;
; 2.424  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[3]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.155     ; 9.062      ;
; 2.424  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[0]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.155     ; 9.062      ;
; 2.456  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[2]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.151     ; 9.034      ;
; 2.469  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[5]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.154     ; 9.018      ;
; 2.545  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 8.926      ;
; 2.545  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 8.926      ;
; 2.681  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[6]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 8.812      ;
; 2.760  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 8.712      ;
; 2.760  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 8.712      ;
; 2.760  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 8.712      ;
; 2.760  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 8.712      ;
; 2.760  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 8.712      ;
; 2.760  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 8.712      ;
; 2.768  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 8.692      ;
; 2.786  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[4]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.698      ;
; 2.786  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[1]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.698      ;
; 2.786  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[7]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.698      ;
; 2.805  ; sdram_reset_n_reg                                                                                                                                                                                  ; SDRAM_ADDR[17]                                                                                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.460       ; -0.107     ; 14.549     ;
; 2.855  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 8.609      ;
; 2.868  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[0]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.616      ;
; 2.868  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[1]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.616      ;
; 2.868  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[2]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.616      ;
; 2.868  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[3]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.616      ;
; 2.868  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[4]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.616      ;
; 2.868  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[5]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.616      ;
; 2.868  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[6]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.616      ;
; 2.868  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[7]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.616      ;
; 2.869  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 8.591      ;
; 2.928  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.553      ;
; 2.928  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.553      ;
; 2.948  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.528      ;
; 2.948  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[1]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.528      ;
; 2.948  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[2]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.528      ;
; 2.948  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.528      ;
; 2.948  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.528      ;
; 2.948  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.528      ;
; 2.948  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.528      ;
; 2.948  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.528      ;
; 2.973  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.508      ;
; 2.973  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[1]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.508      ;
; 2.973  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[2]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.508      ;
; 2.973  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.508      ;
; 2.973  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.508      ;
; 2.973  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.508      ;
; 2.973  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.508      ;
; 2.973  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.508      ;
; 2.993  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.492      ;
; 2.993  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.492      ;
; 2.993  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.492      ;
; 2.993  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.492      ;
; 2.993  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.492      ;
; 2.993  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.492      ;
; 2.993  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.492      ;
; 2.993  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.492      ;
; 2.995  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 8.465      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                         ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.215  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 3.200        ; 3.533      ; 6.829      ;
; 94.602  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 100.000      ; -0.673     ; 4.726      ;
; 96.874  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                       ; FPGA_CLK    ; 100.000      ; 0.468      ; 0.793      ;
; 196.366 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.560      ;
; 196.396 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.530      ;
; 196.488 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.438      ;
; 196.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.415      ;
; 196.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.414      ;
; 196.541 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.385      ;
; 196.542 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.384      ;
; 196.601 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.325      ;
; 196.630 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.296      ;
; 196.634 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.292      ;
; 196.657 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.269      ;
; 196.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.268      ;
; 196.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.268      ;
; 196.687 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.239      ;
; 196.688 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.238      ;
; 196.688 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.238      ;
; 196.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.179      ;
; 196.753 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.173      ;
; 196.776 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.150      ;
; 196.776 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.150      ;
; 196.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.146      ;
; 196.790 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.136      ;
; 196.803 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.123      ;
; 196.804 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.122      ;
; 196.804 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.122      ;
; 196.820 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.106      ;
; 196.833 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.093      ;
; 196.834 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.092      ;
; 196.834 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.092      ;
; 196.893 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.033      ;
; 196.899 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.027      ;
; 196.899 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.027      ;
; 196.922 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.004      ;
; 196.922 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.004      ;
; 196.926 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 3.000      ;
; 196.927 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.999      ;
; 196.936 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.990      ;
; 196.949 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.977      ;
; 196.950 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.976      ;
; 196.950 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.976      ;
; 196.951 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.975      ;
; 196.966 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.960      ;
; 196.979 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.947      ;
; 196.980 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.946      ;
; 196.980 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.946      ;
; 196.981 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.945      ;
; 197.039 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.887      ;
; 197.040 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.886      ;
; 197.045 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.881      ;
; 197.045 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.881      ;
; 197.068 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.858      ;
; 197.068 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.858      ;
; 197.072 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.854      ;
; 197.073 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.853      ;
; 197.073 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.853      ;
; 197.082 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.844      ;
; 197.094 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.832      ;
; 197.095 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.831      ;
; 197.096 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.830      ;
; 197.096 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.830      ;
; 197.097 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.829      ;
; 197.112 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.814      ;
; 197.124 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.802      ;
; 197.125 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.801      ;
; 197.126 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.800      ;
; 197.126 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.800      ;
; 197.127 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.799      ;
; 197.185 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.741      ;
; 197.186 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.740      ;
; 197.186 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.740      ;
; 197.191 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.735      ;
; 197.191 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.735      ;
; 197.214 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.712      ;
; 197.214 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.712      ;
; 197.218 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.708      ;
; 197.219 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.707      ;
; 197.219 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.707      ;
; 197.219 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.707      ;
; 197.228 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.698      ;
; 197.238 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.684      ;
; 197.240 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.686      ;
; 197.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.681      ;
; 197.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.685      ;
; 197.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.684      ;
; 197.243 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.683      ;
; 197.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.668      ;
; 197.270 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.656      ;
; 197.271 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.651      ;
; 197.271 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.655      ;
; 197.272 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.654      ;
; 197.272 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.654      ;
; 197.273 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.653      ;
; 197.330 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.596      ;
; 197.331 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.595      ;
; 197.332 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.594      ;
; 197.332 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.594      ;
; 197.337 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.075     ; 2.589      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                      ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                   ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.190 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.240      ; 1.472      ;
; -0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.240      ; 1.469      ;
; -0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.240      ; 1.468      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.240      ; 1.454      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.240      ; 1.454      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.240      ; 1.447      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.240      ; 1.441      ;
; -0.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.217      ; 1.298      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.218      ; 1.298      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.218      ; 1.298      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.217      ; 1.297      ;
; -0.030 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.218      ; 1.290      ;
; -0.030 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.217      ; 1.289      ;
; -0.030 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.218      ; 1.290      ;
; -0.029 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.227      ; 1.298      ;
; -0.029 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.228      ; 1.299      ;
; -0.028 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.219      ; 1.289      ;
; -0.028 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.227      ; 1.297      ;
; -0.028 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.228      ; 1.298      ;
; -0.027 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.228      ; 1.297      ;
; -0.027 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.219      ; 1.288      ;
; -0.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.228      ; 1.296      ;
; -0.025 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.231      ; 1.298      ;
; -0.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.227      ; 1.289      ;
; -0.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.228      ; 1.290      ;
; -0.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.228      ; 1.289      ;
; -0.017 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.214      ; 1.273      ;
; -0.016 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.231      ; 1.289      ;
; -0.015 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.231      ; 1.288      ;
; -0.015 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.241      ; 1.298      ;
; -0.013 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.232      ; 1.287      ;
; -0.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.232      ; 1.286      ;
; -0.003 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.228      ; 1.273      ;
; -0.002 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.232      ; 1.276      ;
; 0.005  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.227      ; 1.264      ;
; 0.006  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.228      ; 1.264      ;
; 0.009  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.227      ; 1.260      ;
; 0.015  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.227      ; 1.254      ;
; 0.150  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.227      ; 1.119      ;
; 0.151  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.227      ; 1.118      ;
; 12.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.567     ; 7.705      ;
; 12.604 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.567     ; 7.663      ;
; 12.612 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.149      ;
; 12.634 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.127      ;
; 12.637 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.567     ; 7.630      ;
; 12.654 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.107      ;
; 12.676 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.085      ;
; 12.678 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.083      ;
; 12.687 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.074      ;
; 12.709 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.052      ;
; 12.720 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.041      ;
; 12.753 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 8.008      ;
; 12.775 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.986      ;
; 12.817 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.944      ;
; 12.850 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.911      ;
; 12.854 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.907      ;
; 12.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.865      ;
; 12.929 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.832      ;
; 13.202 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.559      ;
; 13.244 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.517      ;
; 13.277 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.484      ;
; 13.316 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.452      ;
; 13.358 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.410      ;
; 13.391 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.377      ;
; 13.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.083     ; 6.740      ;
; 13.983 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.083     ; 6.768      ;
; 14.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.757      ;
; 14.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.715      ;
; 14.079 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.682      ;
; 14.190 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.083     ; 6.431      ;
; 14.285 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.476      ;
; 14.327 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.434      ;
; 14.334 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 6.420      ;
; 14.360 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.401      ;
; 14.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 6.392      ;
; 14.367 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.083     ; 6.254      ;
; 14.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.085     ; 6.231      ;
; 14.404 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.074     ; 6.356      ;
; 14.446 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.074     ; 6.314      ;
; 14.467 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.294      ;
; 14.479 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.074     ; 6.281      ;
; 14.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 6.250      ;
; 14.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.252      ;
; 14.510 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 6.244      ;
; 14.529 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 6.226      ;
; 14.539 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 6.213      ;
; 14.542 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 6.219      ;
; 14.545 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.083     ; 6.206      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
; 14.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.090     ; 6.163      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                             ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.070 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.149     ; 4.472      ;
; 1.166 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.149     ; 4.376      ;
; 1.262 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 4.266      ;
; 1.338 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.148     ; 4.205      ;
; 1.358 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.161     ; 4.172      ;
; 1.371 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 4.157      ;
; 1.388 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.149     ; 4.154      ;
; 1.404 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.144     ; 4.143      ;
; 1.414 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.150     ; 4.127      ;
; 1.414 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.150     ; 4.127      ;
; 1.447 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.148     ; 4.096      ;
; 1.451 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.149     ; 4.091      ;
; 1.457 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 4.071      ;
; 1.457 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 4.071      ;
; 1.457 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 4.071      ;
; 1.457 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 4.071      ;
; 1.467 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.161     ; 4.063      ;
; 1.497 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.149     ; 4.045      ;
; 1.523 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.150     ; 4.018      ;
; 1.523 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.150     ; 4.018      ;
; 1.560 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.149     ; 3.982      ;
; 1.566 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 3.962      ;
; 1.566 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 3.962      ;
; 1.566 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 3.962      ;
; 1.566 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 3.962      ;
; 1.669 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.154     ; 3.868      ;
; 1.840 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.161     ; 3.690      ;
; 1.867 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 3.788      ;
; 1.881 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.145     ; 3.665      ;
; 1.942 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.712      ;
; 1.942 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.712      ;
; 1.949 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.161     ; 3.581      ;
; 1.976 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.164     ; 3.681      ;
; 1.978 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.154     ; 3.559      ;
; 1.979 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.164     ; 3.678      ;
; 1.979 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.164     ; 3.678      ;
; 1.985 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.669      ;
; 1.986 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.668      ;
; 1.988 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 3.667      ;
; 2.012 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.173     ; 3.636      ;
; 2.012 ; SDRAM_READ_ENABLE       ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.173     ; 3.636      ;
; 2.014 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 3.641      ;
; 2.019 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 3.636      ;
; 2.020 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.164     ; 3.637      ;
; 2.021 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 3.634      ;
; 2.077 ; SDRAM_ADDR[7]           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.161     ; 3.453      ;
; 2.090 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.159     ; 3.442      ;
; 2.122 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.532      ;
; 2.123 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.531      ;
; 2.124 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.530      ;
; 2.154 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.155     ; 3.382      ;
; 2.154 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 3.374      ;
; 2.164 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.155     ; 3.372      ;
; 2.168 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 3.360      ;
; 2.277 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.163     ; 3.251      ;
; 2.371 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.176     ; 3.144      ;
; 2.501 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.169     ; 3.021      ;
; 2.510 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.183     ; 3.128      ;
; 2.512 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.183     ; 3.126      ;
; 2.529 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.122      ;
; 2.529 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.122      ;
; 2.529 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.122      ;
; 2.529 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.122      ;
; 2.529 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.122      ;
; 2.529 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.122      ;
; 2.529 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.122      ;
; 2.583 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.160     ; 2.948      ;
; 2.612 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.161     ; 2.918      ;
; 2.613 ; SDRAM_ADDR[0]           ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.181     ; 3.027      ;
; 2.628 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.171     ; 2.892      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.661 ; SDRAM_READ_ENABLE       ; ram_do_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 2.994      ;
; 2.688 ; SDRAM_ADDR[0]           ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.181     ; 2.952      ;
; 2.721 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.160     ; 2.810      ;
; 2.723 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.176     ; 2.922      ;
; 2.731 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.171     ; 2.789      ;
; 2.740 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.171     ; 2.780      ;
; 2.743 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.176     ; 2.902      ;
; 2.754 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.174     ; 2.893      ;
; 2.798 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.176     ; 2.847      ;
; 2.847 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.804      ;
; 2.847 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.804      ;
; 2.847 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.804      ;
; 2.847 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.804      ;
; 2.847 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.804      ;
; 2.847 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.804      ;
; 2.847 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.804      ;
; 2.847 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.804      ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                 ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.353  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 7.898      ;
; 9.387  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 7.863      ;
; 9.644  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.116     ; 7.571      ;
; 9.708  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 7.542      ;
; 9.765  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 7.485      ;
; 9.793  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 7.413      ;
; 9.818  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 7.432      ;
; 9.910  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 7.341      ;
; 9.925  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.116     ; 7.290      ;
; 9.940  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 7.276      ;
; 10.009 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.094     ; 7.228      ;
; 10.022 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.093     ; 7.216      ;
; 10.028 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.094     ; 7.209      ;
; 10.056 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 7.195      ;
; 10.099 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 7.151      ;
; 10.103 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.116     ; 7.112      ;
; 10.115 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.128     ; 7.088      ;
; 10.175 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.129     ; 7.027      ;
; 10.181 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 7.070      ;
; 10.188 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 7.062      ;
; 10.213 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.116     ; 7.002      ;
; 10.220 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 7.031      ;
; 10.240 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 7.011      ;
; 10.246 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 6.960      ;
; 10.317 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 6.933      ;
; 10.339 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.912      ;
; 10.340 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 6.876      ;
; 10.359 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 6.891      ;
; 10.362 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.093     ; 6.876      ;
; 10.364 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.093     ; 6.874      ;
; 10.376 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.875      ;
; 10.398 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_event_reg                                                                                           ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.182     ; 6.881      ;
; 10.400 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.485     ; 6.576      ;
; 10.418 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 6.788      ;
; 10.433 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.818      ;
; 10.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.485     ; 6.503      ;
; 10.497 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.485     ; 6.479      ;
; 10.511 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 6.695      ;
; 10.542 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.709      ;
; 10.586 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 6.664      ;
; 10.590 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[4]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.182     ; 6.689      ;
; 10.628 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.623      ;
; 10.630 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.621      ;
; 10.644 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.093     ; 6.594      ;
; 10.647 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 6.569      ;
; 10.647 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.485     ; 6.329      ;
; 10.676 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 6.574      ;
; 10.683 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.568      ;
; 10.700 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.485     ; 6.276      ;
; 10.721 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 6.485      ;
; 10.751 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.485     ; 6.225      ;
; 10.775 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.485     ; 6.201      ;
; 10.850 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.116     ; 6.365      ;
; 10.914 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 6.292      ;
; 10.926 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 6.290      ;
; 10.947 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.485     ; 6.029      ;
; 10.972 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.279      ;
; 10.975 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.276      ;
; 10.980 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.271      ;
; 11.025 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.226      ;
; 11.027 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.166      ;
; 11.104 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.147      ;
; 11.154 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 6.097      ;
; 11.163 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[1]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.182     ; 6.116      ;
; 11.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.006      ;
; 11.298 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.093     ; 5.940      ;
; 11.319 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 5.932      ;
; 11.327 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.471     ; 5.663      ;
; 11.359 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 5.892      ;
; 11.362 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[8]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 5.918      ;
; 11.387 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 5.819      ;
; 11.389 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 5.817      ;
; 11.401 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[7]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 5.879      ;
; 11.431 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 5.820      ;
; 11.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 5.781      ;
; 11.488 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 5.728      ;
; 11.497 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 5.754      ;
; 11.505 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                                                                                                                      ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.176     ; 5.780      ;
; 11.511 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[6]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.188     ; 5.762      ;
; 11.547 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 5.704      ;
; 11.557 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 5.649      ;
; 11.559 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.472     ; 5.430      ;
; 11.638 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                                                                                                     ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.176     ; 5.647      ;
; 11.642 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.125     ; 5.564      ;
; 11.663 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.473     ; 5.325      ;
; 11.694 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 5.556      ;
; 11.698 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                                                                                                                      ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.176     ; 5.587      ;
; 11.728 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.471     ; 5.262      ;
; 11.755 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.471     ; 5.235      ;
; 11.759 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.471     ; 5.231      ;
; 11.775 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[2]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 5.505      ;
; 11.869 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 5.381      ;
; 11.885 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.472     ; 5.104      ;
; 11.918 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.472     ; 5.071      ;
; 11.919 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.472     ; 5.070      ;
; 11.927 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 5.324      ;
; 11.943 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[5]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.188     ; 5.330      ;
; 11.954 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 5.296      ;
; 11.967 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.473     ; 5.021      ;
; 11.989 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 5.262      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                   ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.918 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.017      ;
; -1.918 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.017      ;
; -1.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.034      ;
; -1.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.034      ;
; -1.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.544      ; 1.035      ;
; -1.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.549      ; 1.043      ;
; -1.895 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.549      ; 1.044      ;
; -1.891 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.558      ; 1.057      ;
; -1.888 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.531      ; 1.033      ;
; -1.882 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.549      ; 1.057      ;
; -1.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.549      ; 1.058      ;
; -1.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.549      ; 1.058      ;
; -1.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.549      ; 1.058      ;
; -1.879 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.056      ;
; -1.879 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.056      ;
; -1.878 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.544      ; 1.056      ;
; -1.878 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.544      ; 1.056      ;
; -1.877 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.544      ; 1.057      ;
; -1.877 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.544      ; 1.057      ;
; -1.876 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.059      ;
; -1.876 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.059      ;
; -1.876 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.544      ; 1.058      ;
; -1.869 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.536      ; 1.057      ;
; -1.868 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.536      ; 1.058      ;
; -1.867 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.535      ; 1.058      ;
; -1.866 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.535      ; 1.059      ;
; -1.866 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.534      ; 1.058      ;
; -1.864 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.534      ; 1.060      ;
; -1.819 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.534      ; 1.105      ;
; -1.818 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.534      ; 1.106      ;
; -1.816 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.534      ; 1.108      ;
; -1.766 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.169      ;
; -1.738 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.545      ; 1.197      ;
; -1.703 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.557      ; 1.244      ;
; -1.696 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.557      ; 1.251      ;
; -1.694 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.557      ; 1.253      ;
; -1.694 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.557      ; 1.253      ;
; -1.676 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.557      ; 1.271      ;
; -1.675 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.557      ; 1.272      ;
; -1.560 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.557      ; 1.387      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                    ; To Node                                                                                                                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[4]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                        ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                           ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                   ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                   ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[0]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[1]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[2]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[7]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[7]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[8]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[8]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[9]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[9]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[10]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[10]                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_insn_fetch                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_insn_fetch                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; paddle_mode_reg                                                                                                                              ; paddle_mode_reg                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[7]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[7]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[7]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[7]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[5]                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[5]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[3]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[3]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|command_reg                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|command_reg                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[0]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                         ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; scanlines_reg                                                                                   ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.746      ;
; 0.466 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.758      ;
; 0.494 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.786      ;
; 0.495 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.787      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.792      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.797      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.797      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.797      ;
; 0.517 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.809      ;
; 0.686 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.978      ;
; 0.686 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.979      ;
; 0.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.979      ;
; 0.690 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.982      ;
; 0.694 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.986      ;
; 0.696 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.988      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.990      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.990      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.990      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.991      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.991      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.991      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.991      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.991      ;
; 0.700 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.992      ;
; 0.700 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.992      ;
; 0.700 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.992      ;
; 0.700 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.992      ;
; 0.700 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.992      ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.468 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.758      ;
; 0.503 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.794      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.796      ;
; 0.528 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.819      ;
; 0.541 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.831      ;
; 0.670 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.961      ;
; 0.672 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.963      ;
; 0.693 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.984      ;
; 0.708 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.999      ;
; 0.715 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.006      ;
; 0.717 ; seq_reg[10]                                               ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.008      ;
; 0.726 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.016      ;
; 0.735 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.025      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.030      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.030      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.031      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.031      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.031      ;
; 0.742 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.032      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.032      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.743 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.033      ;
; 0.744 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.034      ;
; 0.748 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.038      ;
; 0.759 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.049      ;
; 0.762 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.053      ;
; 0.763 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.053      ;
; 0.803 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.094      ;
; 0.846 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.137      ;
; 0.899 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.190      ;
; 1.017 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.307      ;
; 1.026 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.317      ;
; 1.054 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.345      ;
; 1.057 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.348      ;
; 1.062 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.352      ;
; 1.067 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.357      ;
; 1.094 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.384      ;
; 1.095 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.385      ;
; 1.095 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.385      ;
; 1.096 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.386      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.391      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.392      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.394      ;
; 1.105 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.395      ;
; 1.106 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.396      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.400      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.401      ;
; 1.113 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.403      ;
; 1.114 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.404      ;
; 1.115 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.405      ;
; 1.116 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.399      ;
; 1.171 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.461      ;
; 1.204 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.494      ;
; 1.217 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.507      ;
; 1.225 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.515      ;
; 1.226 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.517      ;
; 1.227 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.517      ;
; 1.234 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.524      ;
; 1.235 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.525      ;
; 1.236 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.526      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.531      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.532      ;
; 1.245 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.535      ;
; 1.246 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.536      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.540      ;
; 1.251 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.541      ;
; 1.254 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.544      ;
; 1.255 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.545      ;
; 1.262 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.554      ;
; 1.282 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 1.581      ;
; 1.304 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.596      ;
; 1.308 ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.258      ; 1.778      ;
; 1.310 ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.258      ; 1.780      ;
; 1.316 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 1.611      ;
; 1.335 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.623      ;
; 1.336 ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.259      ; 1.807      ;
; 1.338 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.626      ;
; 1.342 ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.254      ; 1.808      ;
; 1.342 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 1.637      ;
; 1.346 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.083      ; 1.641      ;
; 1.365 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.655      ;
; 1.366 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.656      ;
; 1.374 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.664      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                            ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                       ; To Node                                                                         ; Launch Clock                                                                   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.494 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.785      ;
; 0.502 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.793      ;
; 0.503 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.794      ;
; 0.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.750 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.041      ;
; 0.750 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.041      ;
; 0.751 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.042      ;
; 0.751 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.042      ;
; 0.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.054      ;
; 0.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.055      ;
; 0.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.055      ;
; 0.765 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.056      ;
; 0.766 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.057      ;
; 0.768 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.059      ;
; 0.773 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.064      ;
; 1.101 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.392      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.103 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.394      ;
; 1.104 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.395      ;
; 1.105 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.083      ; 1.400      ;
; 1.109 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.110 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.111 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.402      ;
; 1.112 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.403      ;
; 1.112 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.403      ;
; 1.114 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.083      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.119 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.410      ;
; 1.119 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.410      ;
; 1.120 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.411      ;
; 1.120 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.411      ;
; 1.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.412      ;
; 1.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.412      ;
; 1.126 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.417      ;
; 1.129 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.420      ;
; 1.135 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.426      ;
; 1.138 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.429      ;
; 1.200 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.040        ; 4.439      ; 5.991      ;
; 1.228 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.083      ; 1.523      ;
; 1.232 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.523      ;
; 1.232 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.523      ;
; 1.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.234 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.525      ;
; 1.235 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.526      ;
; 1.237 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.083      ; 1.532      ;
; 1.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.532      ;
; 1.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.532      ;
; 1.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.243 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.534      ;
; 1.245 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.083      ; 1.540      ;
; 1.245 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.083      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.250 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.541      ;
; 1.250 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.541      ;
; 1.251 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.542      ;
; 1.251 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.542      ;
; 1.252 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.543      ;
; 1.252 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.543      ;
; 1.254 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.083      ; 1.549      ;
; 1.254 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.083      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
; 1.259 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.550      ;
; 1.259 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.550      ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.480      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.479      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.480      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.480      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[2]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[5]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[3]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.480      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.480      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.479      ;
; 5.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.481      ;
; 5.997 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 5.486      ;
; 5.997 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[0]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 5.484      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.478      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[5]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.478      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[7]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[14]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[7]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[15]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.478      ;
; 5.998 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[5]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.161     ; 5.481      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 5.472      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 5.472      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 5.484      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[30]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[16]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.476      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[16]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.476      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.476      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.467      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 5.484      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 5.484      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.161     ; 5.481      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 5.471      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.467      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[26]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.478      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.478      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.478      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.478      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.161     ; 5.481      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[7]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.479      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_active_reg                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.161     ; 5.481      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.474      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 5.477      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.474      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[19]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.474      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[20]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.474      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.474      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.474      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.474      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.479      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.476      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.476      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.478      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.478      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.467      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[28]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.478      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.476      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.474      ;
; 5.999 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.473      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                         ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.513 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.392     ; 3.594      ;
; 7.513 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.391     ; 3.595      ;
; 7.513 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.391     ; 3.595      ;
; 7.513 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.392     ; 3.594      ;
; 7.513 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.391     ; 3.595      ;
; 7.517 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.390     ; 3.592      ;
; 7.519 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.396     ; 3.584      ;
; 7.519 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.394     ; 3.586      ;
; 7.522 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 3.780      ;
; 7.522 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 3.780      ;
; 7.523 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 3.779      ;
; 7.523 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 3.779      ;
; 7.523 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 3.779      ;
; 7.523 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 3.779      ;
; 7.523 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 3.781      ;
; 7.525 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.264     ; 3.722      ;
; 7.525 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.264     ; 3.722      ;
; 7.525 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.264     ; 3.722      ;
; 7.527 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.265     ; 3.719      ;
; 7.527 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.265     ; 3.719      ;
; 7.533 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.269     ; 3.709      ;
; 7.533 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.267     ; 3.711      ;
; 7.533 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.263     ; 3.715      ;
; 7.537 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.382     ; 3.580      ;
; 7.537 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.382     ; 3.580      ;
; 7.537 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.382     ; 3.580      ;
; 7.538 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.380     ; 3.581      ;
; 7.538 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.380     ; 3.581      ;
; 7.538 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.380     ; 3.581      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.378     ; 3.580      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.382     ; 3.576      ;
; 7.549 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 3.768      ;
; 7.549 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.767      ;
; 7.549 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.767      ;
; 7.550 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.766      ;
; 7.550 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.765      ;
; 7.550 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.765      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.255     ; 3.704      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.255     ; 3.704      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.255     ; 3.704      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.253     ; 3.706      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.253     ; 3.706      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.253     ; 3.706      ;
; 7.553 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.251     ; 3.707      ;
; 7.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.255     ; 3.701      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.806      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.806      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.806      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.806      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.806      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.806      ;
; 7.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.806      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.805      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.805      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.805      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.805      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.805      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.805      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.805      ;
; 7.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.805      ;
; 7.772 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 3.532      ;
; 7.772 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 3.532      ;
; 7.773 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 3.531      ;
; 7.773 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 3.531      ;
; 8.067 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.362      ;
; 8.067 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.362      ;
; 8.067 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.362      ;
; 8.067 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.362      ;
; 8.067 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.362      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 3.361      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 3.360      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 3.363      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 3.360      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 3.363      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 3.360      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 3.360      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 3.360      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 3.363      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 3.360      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 3.363      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 3.360      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 3.360      ;
; 8.068 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 3.364      ;
; 8.069 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.219     ; 3.353      ;
; 8.069 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.219     ; 3.353      ;
; 8.069 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.219     ; 3.353      ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 11.686 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.206     ; 5.439      ;
; 11.699 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.216     ; 5.416      ;
; 11.699 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.216     ; 5.416      ;
; 11.709 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 5.450      ;
; 11.709 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 5.450      ;
; 11.709 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.451      ;
; 11.709 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.451      ;
; 11.709 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.451      ;
; 11.709 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.451      ;
; 11.709 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 5.450      ;
; 11.709 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 5.450      ;
; 11.710 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.450      ;
; 11.710 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.450      ;
; 11.720 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.207     ; 5.404      ;
; 12.250 ; sdram_reset_n_reg ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.043      ;
; 12.253 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.159     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.037      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.254 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.158     ; 5.049      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 5.035      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
; 12.255 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.036      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.740 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 3.134      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 3.134      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 3.134      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 3.134      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 3.134      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 3.134      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 3.134      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 3.137      ;
; 2.740 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 3.134      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.144      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 3.145      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 3.145      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 3.145      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.143      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.144      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.143      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.143      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.144      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.143      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.143      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.144      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.143      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.144      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.144      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.143      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.147      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 3.145      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 3.137      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.144      ;
; 2.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.160      ; 3.137      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.160      ; 3.137      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.160      ; 3.137      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.160      ; 3.137      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 3.144      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.160      ; 3.137      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 3.143      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 3.146      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 3.146      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 3.146      ;
; 2.745 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 3.146      ;
; 2.976 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 3.300      ;
; 2.976 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 3.300      ;
; 2.977 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 3.300      ;
; 2.977 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 3.300      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 3.543      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 3.544      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 3.544      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 3.544      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 3.544      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 3.543      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 3.543      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 3.544      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 3.543      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 3.543      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 3.544      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 3.543      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 3.543      ;
; 3.148 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 3.544      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.756      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.313 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.755      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.756      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.314 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.757      ;
; 4.315 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.223      ; 4.770      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.758      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.758      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.758      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.758      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.758      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.758      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.758      ;
; 4.315 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.758      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                         ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.770 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[0]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.225      ;
; 4.770 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[1]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.225      ;
; 4.770 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[2]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.225      ;
; 4.770 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[7]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.225      ;
; 4.770 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[8]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.225      ;
; 4.770 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[9]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.225      ;
; 4.770 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[10]                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.225      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.226      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.226      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.226      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.226      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.231      ; 5.234      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.224      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.224      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.224      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.224      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.224      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.224      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.224      ;
; 4.771 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.224      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.225      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 5.226      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.225      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 5.221      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 5.221      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 5.223      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 5.223      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 5.223      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 5.223      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 5.225      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 5.222      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 5.223      ;
; 4.772 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 5.223      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 5.222      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.773 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[17]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.225      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[2]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 5.239      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 5.239      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 5.239      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 5.239      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 5.239      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 5.239      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[0]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[1]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[2]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[3]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[4]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[5]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[6]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[7]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqen_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 5.239      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqen_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqen_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 5.239      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqen_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.238      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.236      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.236      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 5.236      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 5.231      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 5.232      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 5.231      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 5.231      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 5.232      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 5.231      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 5.232      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 5.232      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 5.239      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.608 ; 5.766        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.608 ; 5.766        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.608 ; 5.766        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                              ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                          ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                         ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.108 ; 10.328       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010                  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100                  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101                  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]                        ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]                     ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]                     ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]             ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[1]             ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[2]             ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]             ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[1]             ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[2]             ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]                        ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                        ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                                     ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                    ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|rxStatusMonitor:u_rxStatusMonitor|oldResumeDetected                  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|rxStatusMonitor:u_rxStatusMonitor|resumeIntOut                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000    ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010    ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111    ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000    ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En          ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.028 ; 17.429       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.069 ; 17.470       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.129 ; 17.349       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.129 ; 17.349       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.129 ; 17.349       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.129 ; 17.349       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.129 ; 17.349       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.129 ; 17.349       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.129 ; 17.349       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.131 ; 17.351       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]          ;
; 17.131 ; 17.351       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]          ;
; 17.131 ; 17.351       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ;
; 17.131 ; 17.351       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ;
; 17.131 ; 17.351       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ;
; 17.132 ; 17.352       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.132 ; 17.352       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.132 ; 17.352       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.132 ; 17.352       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.132 ; 17.352       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]          ;
; 17.132 ; 17.352       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]          ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]             ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]       ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]       ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]            ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]      ;
; 17.136 ; 17.356       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]         ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]             ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]             ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]             ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]       ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]       ;
; 17.137 ; 17.357       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]       ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]           ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]           ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]            ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]      ;
; 17.138 ; 17.358       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.141 ; 17.361       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]       ;
; 17.141 ; 17.361       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]           ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]          ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]          ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ;
; 17.149 ; 17.369       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.435 ; 17.435       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.484 ; 17.484       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                       ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 89.439 ; 99.741       ; 10.302         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 89.951 ; 100.253      ; 10.302         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 99.741 ; 99.741       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                      ;
; 99.758 ; 99.946       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.758 ; 99.946       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.758 ; 99.946       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.758 ; 99.946       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.772 ; 99.772       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                        ;
; 99.785 ; 99.785       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                          ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.834 ; 100.054      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.834 ; 100.054      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.834 ; 100.054      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.858 ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                     ;
; 99.858 ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                           ;
; 99.862 ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862 ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.897 ; 99.897       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                   ;
; 99.897 ; 99.897       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                   ;
; 99.897 ; 99.897       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                   ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                    ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                          ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                            ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                          ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                          ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                           ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                          ;
; 99.925 ; 99.925       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                   ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026 ; 3.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 8.420 ; 8.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.654 ; 4.870 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.063 ; 4.343 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.751 ; 5.807 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 6.387 ; 6.337 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 8.420 ; 8.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 7.461 ; 8.050 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.440 ; 4.571 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.536 ; 4.728 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 6.396 ; 6.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 7.293 ; 7.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 7.461 ; 8.050 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.551 ; 6.900 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.526 ; 6.792 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.957 ; 4.166 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864 ; 0.974 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 0.864 ; 0.974 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.045 ; -2.152 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.042 ; -2.149 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.039 ; -2.146 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.050 ; -2.157 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.036 ; -2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.924 ; -3.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.554 ; -3.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.924 ; -3.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -4.547 ; -4.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -5.219 ; -5.164 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.422 ; -3.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -3.089 ; -3.303 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -3.347 ; -3.467 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.443 ; -3.619 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -5.141 ; -5.264 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -6.007 ; -6.015 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.089 ; -3.303 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.382 ; -5.720 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -5.366 ; -5.620 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.885 ; -3.079 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.389 ; 3.932 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.289 ; 3.000 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.284 ; 2.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.293 ; 3.004 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.302 ; 3.013 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.389 ; 3.932 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.303 ; 3.014 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.313 ; 3.024 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.289 ; 3.000 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.376 ; 3.919 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.290 ; 3.001 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.376 ; 3.919 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.388 ; 3.931 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.300 ; 3.011 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.450 ; 3.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.430 ; 3.975 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.425 ; 3.970 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.356 ; 2.151 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.477 ; 3.180 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.486 ; 3.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.608 ; 3.297 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.450 ; 3.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.604 ; 3.293 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.604 ; 3.293 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.594 ; 3.283 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.442 ; 3.987 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.586 ; 3.275 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.596 ; 3.285 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.302 ; 4.647 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.377 ; 3.698 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.302 ; 4.647 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.300 ; 3.011 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.311 ; 3.022 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 8.110 ; 8.248 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 5.192 ; 5.015 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.570 ; 3.386 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.834 ; 7.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.807 ; 4.027 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.089 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.849 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.179 ; 5.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.605 ; 2.568 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.179 ; 5.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.388 ; 2.331 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.170 ; 5.511 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.068 ; 5.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.068 ; 5.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.307 ; 2.183 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.317 ; 2.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.307 ; 2.183 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.057 ; 5.343 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.297 ; 2.173 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.286 ; 2.162 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.296 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.297 ; 2.173 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.287 ; 2.163 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.296 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.422 ; 2.138 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.431 ; 2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.440 ; 2.156 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.573 ; 3.117 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.441 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.451 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.560 ; 3.104 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.572 ; 3.116 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.616 ; 3.162 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.612 ; 3.158 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.615 ; 2.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.623 ; 2.332 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.745 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.636 ; 3.182 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.731 ; 2.426 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.628 ; 3.174 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.723 ; 2.418 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.733 ; 2.428 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.511 ; 2.826 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.511 ; 2.826 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.399 ; 3.737 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.449 ; 2.165 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.184 ; 7.331 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.279 ; 4.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.708 ; 2.528 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.952 ; 6.168 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.932 ; 3.146 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.319 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.083 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.573 ; 1.517 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.790 ; 1.754 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.364 ; 4.706 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.573 ; 1.517 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.355 ; 4.697 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.251 ; 4.538 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.500 ; 1.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.240 ; 4.527 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.469 ; 1.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.469 ; 1.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.479 ; 1.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.480 ; 1.357 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.470 ; 1.347 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.479 ; 1.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.910 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.910 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.910 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.910 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.269 ; 3.269 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.925 ; 2.925 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.294 ; 3.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.314 ; 3.314 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.325 ; 3.325 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.451 ; 4.451 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.129 ; 4.129 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.740 ; 3.740 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.740 ; 3.740 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.730 ; 3.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.359 ; 3.359 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.349 ; 3.349 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.359 ; 3.359 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.907 ; 3.523 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.919 ; 6.535 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 6.919 ; 6.535 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.570 ; 1.599 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.570 ; 1.599 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.570 ; 1.599 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.570 ; 1.599 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.915 ; 1.944 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.585 ; 1.614 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.939 ; 1.968 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.958 ; 1.987 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.969 ; 1.998 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.050 ; 3.079 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.741 ; 2.770 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.367 ; 2.396 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.367 ; 2.396 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.357 ; 2.386 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.001 ; 2.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.991 ; 2.020 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.001 ; 2.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.935 ; 2.567 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.183 ; 5.815 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 6.183 ; 5.815 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.669     ; 2.909     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.669     ; 2.909     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.669     ; 2.909     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.669     ; 2.909     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.974     ; 3.214     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.684     ; 2.924     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.021     ; 3.261     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.047     ; 3.287     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.057     ; 3.297     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.101     ; 4.341     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.811     ; 4.051     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.444     ; 3.684     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.444     ; 3.684     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.434     ; 3.674     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.098     ; 3.338     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.088     ; 3.328     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.098     ; 3.338     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.435     ; 3.819     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.454     ; 6.838     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 6.454     ; 6.838     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.569     ; 1.569     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.569     ; 1.569     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.569     ; 1.569     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.569     ; 1.569     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.863     ; 1.863     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.583     ; 1.583     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.907     ; 1.907     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.932     ; 1.932     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.943     ; 1.943     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.945     ; 2.945     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.666     ; 2.666     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.314     ; 2.314     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.314     ; 2.314     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.304     ; 2.304     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.981     ; 1.981     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.971     ; 1.971     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.981     ; 1.981     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.482     ; 2.850     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.737     ; 6.105     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 5.737     ; 6.105     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                              ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                     ; Note                                           ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
; 36.08 MHz  ; 36.08 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 92.46 MHz  ; 40.0 MHz        ; FPGA_CLK                                                                       ; limit due to minimum period restriction (tmin) ;
; 128.17 MHz ; 128.17 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 128.55 MHz ; 128.55 MHz      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;                                                ;
; 151.95 MHz ; 151.95 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                      ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.174 ; -119.089      ;
; FPGA_CLK                                                                       ; -0.348 ; -0.348        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; -0.267 ; -2.778        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.353  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 9.658  ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                       ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; -1.673 ; -63.841       ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.402  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.402  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.404  ; 0.000         ;
; FPGA_CLK                                                                       ; 0.458  ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                   ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.421  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.854  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 12.097 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                   ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.451 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.854 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.321 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                        ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.519  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.431  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10.071 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.061 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.426 ; 0.000         ;
; FPGA_CLK                                                                       ; 89.470 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; -3.174 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.228     ; 0.991      ;
; -3.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -2.228     ; 0.981      ;
; -2.955 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.789     ; 1.211      ;
; -2.954 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.836     ; 1.163      ;
; -2.850 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.836     ; 1.059      ;
; -2.830 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.836     ; 1.039      ;
; -2.815 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 1.072      ;
; -2.813 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 1.070      ;
; -2.813 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 1.070      ;
; -2.810 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.789     ; 1.066      ;
; -2.784 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.839     ; 0.990      ;
; -2.782 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.839     ; 0.988      ;
; -2.781 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 1.038      ;
; -2.778 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 1.035      ;
; -2.773 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.789     ; 1.029      ;
; -2.756 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.786     ; 1.015      ;
; -2.752 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.786     ; 1.011      ;
; -2.734 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 0.991      ;
; -2.734 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 0.991      ;
; -2.733 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.786     ; 0.992      ;
; -2.722 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.786     ; 0.981      ;
; -2.719 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.786     ; 0.978      ;
; -2.636 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.839     ; 0.842      ;
; -2.617 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.844     ; 0.818      ;
; -2.613 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.839     ; 0.819      ;
; -2.612 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.839     ; 0.818      ;
; -2.611 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.839     ; 0.817      ;
; -2.611 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.839     ; 0.817      ;
; -2.609 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.836     ; 0.818      ;
; -2.602 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.829     ; 0.818      ;
; -2.600 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.829     ; 0.816      ;
; -2.584 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.834     ; 0.795      ;
; -2.584 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.834     ; 0.795      ;
; -2.579 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.829     ; 0.795      ;
; -2.572 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.797     ; 0.820      ;
; -2.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 0.820      ;
; -2.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 0.819      ;
; -2.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 0.819      ;
; -2.561 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.786     ; 0.820      ;
; -2.560 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 0.817      ;
; -2.560 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 0.817      ;
; -2.560 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.786     ; 0.819      ;
; -2.559 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.788     ; 0.816      ;
; -2.546 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.797     ; 0.794      ;
; 2.921  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[6]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.133     ; 8.588      ;
; 2.921  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[3]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.133     ; 8.588      ;
; 2.921  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[0]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.133     ; 8.588      ;
; 2.950  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[2]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.131     ; 8.561      ;
; 2.963  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[5]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.133     ; 8.546      ;
; 3.014  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 8.480      ;
; 3.014  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 8.480      ;
; 3.129  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[6]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.127     ; 8.386      ;
; 3.200  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.282      ;
; 3.227  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 8.268      ;
; 3.227  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 8.268      ;
; 3.227  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 8.268      ;
; 3.227  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 8.268      ;
; 3.227  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 8.268      ;
; 3.227  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 8.268      ;
; 3.260  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[4]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.245      ;
; 3.260  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[1]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.245      ;
; 3.260  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[7]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.245      ;
; 3.277  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 8.206      ;
; 3.284  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.155     ; 8.203      ;
; 3.349  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[0]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.156      ;
; 3.349  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[1]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.156      ;
; 3.349  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[2]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.156      ;
; 3.349  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[3]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.156      ;
; 3.349  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[4]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.156      ;
; 3.349  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[5]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.156      ;
; 3.349  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[6]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.156      ;
; 3.349  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[7]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 8.156      ;
; 3.390  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.112      ;
; 3.390  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.112      ;
; 3.414  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 8.069      ;
; 3.433  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 8.066      ;
; 3.433  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[1]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 8.066      ;
; 3.433  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[2]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 8.066      ;
; 3.433  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 8.066      ;
; 3.433  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 8.066      ;
; 3.433  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 8.066      ;
; 3.433  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 8.066      ;
; 3.433  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 8.066      ;
; 3.451  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.051      ;
; 3.451  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[1]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.051      ;
; 3.451  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[2]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.051      ;
; 3.451  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.051      ;
; 3.451  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.051      ;
; 3.451  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.051      ;
; 3.451  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.051      ;
; 3.451  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 8.051      ;
; 3.461  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.045      ;
; 3.461  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.045      ;
; 3.461  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.045      ;
; 3.461  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.045      ;
; 3.461  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.045      ;
; 3.461  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.045      ;
; 3.461  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.045      ;
; 3.461  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.045      ;
; 3.504  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.136     ; 8.002      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                          ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.348  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 3.200        ; 3.074      ; 6.504      ;
; 94.592  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 100.000      ; -0.809     ; 4.601      ;
; 97.127  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                       ; FPGA_CLK    ; 100.000      ; 0.618      ; 0.744      ;
; 196.791 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 3.144      ;
; 196.830 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 3.105      ;
; 196.877 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 3.058      ;
; 196.916 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 3.019      ;
; 196.917 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 3.018      ;
; 196.955 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.980      ;
; 196.956 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.979      ;
; 196.997 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.938      ;
; 196.999 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.936      ;
; 197.003 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.932      ;
; 197.042 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.893      ;
; 197.043 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.892      ;
; 197.043 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.892      ;
; 197.081 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.854      ;
; 197.082 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.853      ;
; 197.082 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.853      ;
; 197.123 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.812      ;
; 197.123 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.812      ;
; 197.125 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.810      ;
; 197.129 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.806      ;
; 197.132 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.803      ;
; 197.157 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.778      ;
; 197.168 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.767      ;
; 197.169 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.766      ;
; 197.169 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.766      ;
; 197.196 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.739      ;
; 197.207 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.728      ;
; 197.208 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.727      ;
; 197.208 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.727      ;
; 197.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.686      ;
; 197.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.686      ;
; 197.251 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.684      ;
; 197.255 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.680      ;
; 197.255 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.680      ;
; 197.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.677      ;
; 197.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.677      ;
; 197.283 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.652      ;
; 197.294 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.641      ;
; 197.295 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.640      ;
; 197.295 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.640      ;
; 197.297 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.638      ;
; 197.322 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.613      ;
; 197.333 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.602      ;
; 197.334 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.601      ;
; 197.334 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.601      ;
; 197.336 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.599      ;
; 197.375 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.560      ;
; 197.375 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.560      ;
; 197.377 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.558      ;
; 197.378 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.557      ;
; 197.381 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.554      ;
; 197.381 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.554      ;
; 197.381 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.554      ;
; 197.384 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.551      ;
; 197.384 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.551      ;
; 197.409 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.526      ;
; 197.420 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.515      ;
; 197.421 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.514      ;
; 197.421 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.514      ;
; 197.421 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.514      ;
; 197.423 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.512      ;
; 197.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.487      ;
; 197.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.476      ;
; 197.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.475      ;
; 197.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.475      ;
; 197.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.475      ;
; 197.462 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.473      ;
; 197.501 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.434      ;
; 197.501 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.434      ;
; 197.503 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.432      ;
; 197.504 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.431      ;
; 197.504 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.431      ;
; 197.506 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.429      ;
; 197.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.428      ;
; 197.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.428      ;
; 197.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.428      ;
; 197.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.425      ;
; 197.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.425      ;
; 197.535 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.400      ;
; 197.544 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.388      ;
; 197.546 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.389      ;
; 197.547 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.385      ;
; 197.547 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.388      ;
; 197.547 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.388      ;
; 197.549 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.386      ;
; 197.574 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.361      ;
; 197.585 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.350      ;
; 197.586 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.349      ;
; 197.586 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.346      ;
; 197.586 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.349      ;
; 197.586 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.349      ;
; 197.588 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.347      ;
; 197.626 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.306      ;
; 197.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.308      ;
; 197.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.308      ;
; 197.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.308      ;
; 197.629 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.067     ; 2.306      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                      ; To Node                                                                                                                                                                                                   ; Launch Clock                                                                   ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.267 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.089      ; 1.399      ;
; -0.204 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.089      ; 1.336      ;
; -0.202 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.089      ; 1.334      ;
; -0.190 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.089      ; 1.322      ;
; -0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.089      ; 1.319      ;
; -0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.089      ; 1.317      ;
; -0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.089      ; 1.311      ;
; -0.059 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.069      ; 1.171      ;
; -0.058 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.070      ; 1.171      ;
; -0.058 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.070      ; 1.171      ;
; -0.058 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.070      ; 1.171      ;
; -0.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.070      ; 1.165      ;
; -0.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.172      ;
; -0.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.069      ; 1.164      ;
; -0.051 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.171      ;
; -0.051 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.171      ;
; -0.050 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.070      ; 1.163      ;
; -0.050 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.170      ;
; -0.050 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.170      ;
; -0.050 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.070      ; 1.163      ;
; -0.050 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.170      ;
; -0.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.070      ; 1.162      ;
; -0.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.083      ; 1.171      ;
; -0.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.165      ;
; -0.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.163      ;
; -0.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.163      ;
; -0.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.160      ;
; -0.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.068      ; 1.150      ;
; -0.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.083      ; 1.163      ;
; -0.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.083      ; 1.163      ;
; -0.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.082      ; 1.162      ;
; -0.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.082      ; 1.161      ;
; -0.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.092      ; 1.171      ;
; -0.034 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.076      ; 1.153      ;
; -0.030 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.150      ;
; -0.027 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.082      ; 1.152      ;
; -0.023 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.076      ; 1.142      ;
; -0.022 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.142      ;
; 0.094  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.026      ;
; 0.095  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 1.077      ; 1.025      ;
; 13.054 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.532     ; 7.249      ;
; 13.084 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.532     ; 7.219      ;
; 13.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.532     ; 7.182      ;
; 13.126 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.643      ;
; 13.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.627      ;
; 13.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.613      ;
; 13.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.597      ;
; 13.174 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.595      ;
; 13.193 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.576      ;
; 13.204 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.565      ;
; 13.209 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.560      ;
; 13.241 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.528      ;
; 13.247 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.522      ;
; 13.277 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.492      ;
; 13.314 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.455      ;
; 13.347 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.422      ;
; 13.377 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.392      ;
; 13.414 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.355      ;
; 13.655 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.114      ;
; 13.685 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.084      ;
; 13.722 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 7.047      ;
; 13.725 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.060     ; 7.050      ;
; 13.755 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.060     ; 7.020      ;
; 13.792 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.060     ; 6.983      ;
; 14.188 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.074     ; 6.447      ;
; 14.410 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 6.353      ;
; 14.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 6.339      ;
; 14.460 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 6.309      ;
; 14.476 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.074     ; 6.159      ;
; 14.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 6.272      ;
; 14.672 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.074     ; 5.963      ;
; 14.685 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 6.084      ;
; 14.715 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 6.054      ;
; 14.720 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.075     ; 5.914      ;
; 14.722 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 6.041      ;
; 14.725 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 6.038      ;
; 14.752 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 6.017      ;
; 14.836 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 5.933      ;
; 14.844 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.067     ; 5.924      ;
; 14.860 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 5.903      ;
; 14.866 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 5.903      ;
; 14.874 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.067     ; 5.894      ;
; 14.903 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.066     ; 5.866      ;
; 14.911 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.067     ; 5.857      ;
; 14.915 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 5.848      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 5.822      ;
; 14.971 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 5.792      ;
; 14.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.065     ; 5.796      ;
; 14.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.065     ; 5.796      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                              ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.353 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.113     ; 4.230      ;
; 1.445 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.113     ; 4.138      ;
; 1.564 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 4.006      ;
; 1.625 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 3.947      ;
; 1.632 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.108     ; 3.956      ;
; 1.634 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.112     ; 3.950      ;
; 1.668 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.902      ;
; 1.681 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.113     ; 3.902      ;
; 1.699 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 3.883      ;
; 1.699 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 3.883      ;
; 1.729 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 3.853      ;
; 1.729 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 3.843      ;
; 1.738 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.112     ; 3.846      ;
; 1.757 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.813      ;
; 1.757 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.813      ;
; 1.757 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.813      ;
; 1.757 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.813      ;
; 1.785 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.113     ; 3.798      ;
; 1.803 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 3.779      ;
; 1.803 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 3.779      ;
; 1.833 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 3.749      ;
; 1.861 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.709      ;
; 1.861 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.709      ;
; 1.861 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.709      ;
; 1.861 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.709      ;
; 1.902 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.117     ; 3.677      ;
; 2.074 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 3.620      ;
; 2.110 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 3.462      ;
; 2.122 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.109     ; 3.465      ;
; 2.147 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 3.546      ;
; 2.147 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 3.546      ;
; 2.176 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 3.519      ;
; 2.176 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 3.519      ;
; 2.181 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 3.512      ;
; 2.181 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 3.512      ;
; 2.186 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 3.509      ;
; 2.188 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 3.506      ;
; 2.200 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.117     ; 3.379      ;
; 2.203 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 3.491      ;
; 2.205 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 3.490      ;
; 2.214 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 3.358      ;
; 2.215 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 3.479      ;
; 2.218 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 3.476      ;
; 2.228 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.135     ; 3.459      ;
; 2.228 ; SDRAM_READ_ENABLE       ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.135     ; 3.459      ;
; 2.301 ; SDRAM_ADDR[7]           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 3.270      ;
; 2.310 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 3.383      ;
; 2.314 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 3.379      ;
; 2.314 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 3.379      ;
; 2.351 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.123     ; 3.222      ;
; 2.364 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.206      ;
; 2.366 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.118     ; 3.212      ;
; 2.376 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 3.201      ;
; 2.428 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.142      ;
; 2.532 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.038      ;
; 2.588 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 2.970      ;
; 2.699 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.131     ; 2.866      ;
; 2.720 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.132     ; 2.970      ;
; 2.720 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.132     ; 2.970      ;
; 2.720 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.132     ; 2.970      ;
; 2.720 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.132     ; 2.970      ;
; 2.720 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.132     ; 2.970      ;
; 2.720 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.132     ; 2.970      ;
; 2.720 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.132     ; 2.970      ;
; 2.787 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.144     ; 2.891      ;
; 2.788 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.144     ; 2.890      ;
; 2.823 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.740      ;
; 2.824 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 2.747      ;
; 2.827 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 2.744      ;
; 2.830 ; SDRAM_ADDR[0]           ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.142     ; 2.850      ;
; 2.861 ; SDRAM_ADDR[0]           ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.142     ; 2.819      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.867 ; SDRAM_READ_ENABLE       ; ram_do_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.826      ;
; 2.921 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.642      ;
; 2.933 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.630      ;
; 2.941 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 2.631      ;
; 2.944 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 2.741      ;
; 2.956 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 2.729      ;
; 2.980 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 2.706      ;
; 3.033 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.656      ;
; 3.033 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.656      ;
; 3.033 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.656      ;
; 3.033 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.656      ;
; 3.033 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.656      ;
; 3.033 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.656      ;
; 3.033 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.656      ;
; 3.033 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 2.656      ;
; 3.036 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 2.649      ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                 ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.658  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 7.605      ;
; 9.792  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 7.470      ;
; 9.983  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 7.248      ;
; 10.101 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 7.161      ;
; 10.114 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 7.148      ;
; 10.163 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 7.099      ;
; 10.229 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 6.992      ;
; 10.234 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 7.029      ;
; 10.248 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 6.983      ;
; 10.334 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 6.918      ;
; 10.343 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 6.908      ;
; 10.367 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.896      ;
; 10.413 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 6.818      ;
; 10.451 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 6.800      ;
; 10.454 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 6.808      ;
; 10.465 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.116     ; 6.755      ;
; 10.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 6.762      ;
; 10.489 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.774      ;
; 10.499 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 6.763      ;
; 10.499 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.764      ;
; 10.537 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.116     ; 6.683      ;
; 10.551 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.712      ;
; 10.637 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.626      ;
; 10.644 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 6.608      ;
; 10.660 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 6.571      ;
; 10.665 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 6.566      ;
; 10.692 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 6.560      ;
; 10.695 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 6.526      ;
; 10.707 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 6.555      ;
; 10.725 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.538      ;
; 10.741 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 6.521      ;
; 10.747 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.516      ;
; 10.820 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_event_reg                                                                                           ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.162     ; 6.480      ;
; 10.823 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.440      ;
; 10.839 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 6.382      ;
; 10.878 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[4]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.162     ; 6.422      ;
; 10.892 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.427     ; 6.143      ;
; 10.926 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 6.295      ;
; 10.927 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.336      ;
; 10.949 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 6.313      ;
; 10.950 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 6.302      ;
; 10.952 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.311      ;
; 10.966 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.427     ; 6.069      ;
; 10.989 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 6.242      ;
; 10.994 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.427     ; 6.041      ;
; 10.995 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 6.267      ;
; 11.028 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 6.193      ;
; 11.084 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.179      ;
; 11.148 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.427     ; 5.887      ;
; 11.170 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.427     ; 5.865      ;
; 11.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 6.037      ;
; 11.238 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.427     ; 5.797      ;
; 11.244 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.019      ;
; 11.247 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 6.016      ;
; 11.251 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 5.970      ;
; 11.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.427     ; 5.769      ;
; 11.290 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.973      ;
; 11.292 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.971      ;
; 11.325 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.126     ; 5.885      ;
; 11.403 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.860      ;
; 11.426 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.427     ; 5.609      ;
; 11.441 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 5.790      ;
; 11.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.761      ;
; 11.531 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.126     ; 5.679      ;
; 11.590 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.673      ;
; 11.611 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 5.641      ;
; 11.629 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[1]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.162     ; 5.671      ;
; 11.633 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.630      ;
; 11.647 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 5.574      ;
; 11.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.576      ;
; 11.694 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 5.527      ;
; 11.710 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.553      ;
; 11.749 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.514      ;
; 11.751 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 5.480      ;
; 11.803 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.460      ;
; 11.806 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[8]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 5.495      ;
; 11.810 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 5.240      ;
; 11.840 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 5.381      ;
; 11.853 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[7]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 5.448      ;
; 11.927 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[6]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.167     ; 5.368      ;
; 11.927 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 5.294      ;
; 11.938 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                                                                                                                      ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.157     ; 5.367      ;
; 11.960 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                                                                                                                      ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.159     ; 5.343      ;
; 11.977 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 5.285      ;
; 12.030 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.417     ; 5.015      ;
; 12.060 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                                                                                                     ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.157     ; 5.245      ;
; 12.114 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 5.148      ;
; 12.120 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[2]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 5.181      ;
; 12.120 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.417     ; 4.925      ;
; 12.191 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 4.859      ;
; 12.202 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 5.061      ;
; 12.214 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 4.836      ;
; 12.219 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 4.831      ;
; 12.237 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.074     ; 5.025      ;
; 12.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.105     ; 4.965      ;
; 12.284 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[5]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.167     ; 5.011      ;
; 12.302 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 4.961      ;
; 12.337 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 4.926      ;
; 12.337 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.417     ; 4.708      ;
; 12.366 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.417     ; 4.679      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                   ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.673 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.935      ;
; -1.672 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.936      ;
; -1.652 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.956      ;
; -1.650 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.240      ; 0.963      ;
; -1.650 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.958      ;
; -1.649 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.234      ; 0.958      ;
; -1.648 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.251      ; 0.976      ;
; -1.647 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.240      ; 0.966      ;
; -1.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.226      ; 0.955      ;
; -1.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.241      ; 0.976      ;
; -1.636 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.241      ; 0.978      ;
; -1.635 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.241      ; 0.979      ;
; -1.635 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.240      ; 0.978      ;
; -1.633 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.975      ;
; -1.633 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.975      ;
; -1.633 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.975      ;
; -1.632 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.976      ;
; -1.632 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.976      ;
; -1.631 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.977      ;
; -1.629 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.979      ;
; -1.629 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.979      ;
; -1.628 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 0.980      ;
; -1.623 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.227      ; 0.977      ;
; -1.623 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.228      ; 0.978      ;
; -1.622 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.228      ; 0.979      ;
; -1.622 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.226      ; 0.977      ;
; -1.621 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.227      ; 0.979      ;
; -1.619 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.226      ; 0.980      ;
; -1.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.227      ; 1.020      ;
; -1.579 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.227      ; 1.021      ;
; -1.576 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.227      ; 1.024      ;
; -1.539 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.234      ; 1.068      ;
; -1.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.235      ; 1.111      ;
; -1.490 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.246      ; 1.129      ;
; -1.483 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.246      ; 1.136      ;
; -1.480 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.246      ; 1.139      ;
; -1.478 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.246      ; 1.141      ;
; -1.466 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.246      ; 1.153      ;
; -1.461 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.246      ; 1.158      ;
; -1.373 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 2.246      ; 1.246      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter2|out_reg                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter2|out_reg                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[4]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[2]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[2]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[0]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[0]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1|out_reg                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1|out_reg                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|highpass1_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|highpass1_reg                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[0]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[0]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[1]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[1]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[2]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[2]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[7]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[7]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[8]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[8]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[9]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[9]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[10]                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[10]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_insn_fetch                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_insn_fetch                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; paddle_mode_reg                                                                                                                                            ; paddle_mode_reg                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[1]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[0]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]               ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[2]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[0]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[1]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[3]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[6]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[6]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[5]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[5]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[7]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[7]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]               ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[0]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[2]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[3]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[5]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[5]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[7]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[7]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                          ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; scanlines_reg                                                                                   ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.684      ;
; 0.455 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.722      ;
; 0.457 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.724      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.735      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.735      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.740      ;
; 0.480 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.746      ;
; 0.609 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.876      ;
; 0.610 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.876      ;
; 0.611 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.877      ;
; 0.614 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.880      ;
; 0.621 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.887      ;
; 0.623 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.889      ;
; 0.644 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.910      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.911      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.647 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.913      ;
; 0.647 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.913      ;
; 0.647 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.913      ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.405 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.405 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.405 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.419 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.684      ;
; 0.420 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.684      ;
; 0.472 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.737      ;
; 0.473 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.738      ;
; 0.494 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.759      ;
; 0.499 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.763      ;
; 0.620 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.885      ;
; 0.622 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.887      ;
; 0.629 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.894      ;
; 0.661 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.925      ;
; 0.664 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.929      ;
; 0.664 ; seq_reg[10]                                               ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.929      ;
; 0.668 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.933      ;
; 0.674 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.938      ;
; 0.686 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.951      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.952      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.954      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.954      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.954      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.955      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.955      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.956      ;
; 0.694 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.958      ;
; 0.694 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.958      ;
; 0.696 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.961      ;
; 0.711 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.976      ;
; 0.712 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.976      ;
; 0.713 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.977      ;
; 0.747 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.012      ;
; 0.802 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.067      ;
; 0.832 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.097      ;
; 0.896 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.160      ;
; 0.949 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.214      ;
; 0.952 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.217      ;
; 0.955 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.971 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.235      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.240      ;
; 1.004 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.261      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.272      ;
; 1.009 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.273      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.274      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.275      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.275      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.275      ;
; 1.014 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.278      ;
; 1.015 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.279      ;
; 1.015 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.279      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.287      ;
; 1.024 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.288      ;
; 1.028 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.292      ;
; 1.028 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.292      ;
; 1.028 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.292      ;
; 1.058 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.323      ;
; 1.092 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.357      ;
; 1.097 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.362      ;
; 1.097 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.362      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.367      ;
; 1.108 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.372      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.373      ;
; 1.127 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.392      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.394      ;
; 1.131 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.395      ;
; 1.132 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.396      ;
; 1.133 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.397      ;
; 1.133 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.397      ;
; 1.136 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.400      ;
; 1.137 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.401      ;
; 1.141 ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.238      ; 1.574      ;
; 1.143 ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.238      ; 1.576      ;
; 1.145 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.409      ;
; 1.146 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.410      ;
; 1.150 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.414      ;
; 1.150 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.414      ;
; 1.160 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.425      ;
; 1.161 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.434      ;
; 1.174 ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.238      ; 1.607      ;
; 1.185 ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.234      ; 1.614      ;
; 1.195 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 1.457      ;
; 1.198 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.467      ;
; 1.200 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.469      ;
; 1.204 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.473      ;
; 1.217 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.480      ;
; 1.225 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.489      ;
; 1.230 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.494      ;
; 1.235 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.502      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                           ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                       ; To Node                                                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.723      ;
; 0.470 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.736      ;
; 0.471 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.737      ;
; 0.694 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.959      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.962      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.962      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.962      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.962      ;
; 0.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.963      ;
; 0.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.963      ;
; 0.699 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.964      ;
; 0.701 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.966      ;
; 0.701 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.966      ;
; 0.703 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.968      ;
; 0.709 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.974      ;
; 0.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.976      ;
; 0.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.976      ;
; 0.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.976      ;
; 0.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.977      ;
; 0.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.980      ;
; 0.724 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.989      ;
; 1.013 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.281      ;
; 1.015 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.280      ;
; 1.015 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.280      ;
; 1.015 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.280      ;
; 1.016 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.281      ;
; 1.017 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.282      ;
; 1.018 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.283      ;
; 1.018 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.283      ;
; 1.018 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.283      ;
; 1.020 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.285      ;
; 1.020 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.285      ;
; 1.020 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.285      ;
; 1.020 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.285      ;
; 1.021 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.286      ;
; 1.021 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.286      ;
; 1.021 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.286      ;
; 1.022 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.287      ;
; 1.022 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.287      ;
; 1.028 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.296      ;
; 1.030 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.295      ;
; 1.030 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.295      ;
; 1.030 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.295      ;
; 1.030 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.295      ;
; 1.031 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.296      ;
; 1.031 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.296      ;
; 1.032 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.297      ;
; 1.033 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.298      ;
; 1.035 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.300      ;
; 1.035 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.300      ;
; 1.035 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.300      ;
; 1.035 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.300      ;
; 1.036 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.301      ;
; 1.037 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.302      ;
; 1.045 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.310      ;
; 1.049 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.314      ;
; 1.115 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.380      ;
; 1.115 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.383      ;
; 1.116 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.381      ;
; 1.116 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.381      ;
; 1.117 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.382      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.383      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.383      ;
; 1.120 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.385      ;
; 1.124 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.389      ;
; 1.129 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.394      ;
; 1.129 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.394      ;
; 1.130 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.395      ;
; 1.134 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.402      ;
; 1.135 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.403      ;
; 1.137 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.402      ;
; 1.137 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.402      ;
; 1.138 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.403      ;
; 1.140 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.408      ;
; 1.140 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.405      ;
; 1.140 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.405      ;
; 1.140 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.405      ;
; 1.142 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.407      ;
; 1.142 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.407      ;
; 1.142 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.407      ;
; 1.142 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.407      ;
; 1.143 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.408      ;
; 1.143 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.408      ;
; 1.144 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.409      ;
; 1.149 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.417      ;
; 1.150 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.418      ;
; 1.152 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.417      ;
; 1.152 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.417      ;
; 1.152 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.417      ;
; 1.153 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.418      ;
; 1.153 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.418      ;
; 1.154 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.419      ;
; 1.155 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.420      ;
; 1.157 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.422      ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                             ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                          ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[5]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[26]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[28]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[26]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[7]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[29]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[25]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[14]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[7]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[15]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.078      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[5]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.421 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.077      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.139     ; 5.081      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 5.072      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 5.072      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[16]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.142     ; 5.078      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.077      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.142     ; 5.078      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.077      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.143     ; 5.077      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.142     ; 5.078      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 5.067      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.137     ; 5.083      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.139     ; 5.081      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.142     ; 5.078      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.142     ; 5.078      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.071      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 5.067      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.142     ; 5.078      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[24]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[2]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[3]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.138     ; 5.082      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_clock_last_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[3]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[1]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[2]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 5.075      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[2]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[3]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[9]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 5.074      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 5.074      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[6]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.144     ; 5.076      ;
; 6.422 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.142     ; 5.078      ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                          ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 3.473      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 3.473      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 3.473      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 3.473      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 3.475      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 3.473      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 3.473      ;
; 7.861 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.360     ; 3.284      ;
; 7.862 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.356     ; 3.287      ;
; 7.862 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.356     ; 3.287      ;
; 7.862 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.356     ; 3.287      ;
; 7.865 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.356     ; 3.284      ;
; 7.866 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.357     ; 3.282      ;
; 7.866 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.361     ; 3.278      ;
; 7.867 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.363     ; 3.275      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.462      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.460      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.460      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.460      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.176     ; 3.461      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.176     ; 3.461      ;
; 7.883 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.349     ; 3.273      ;
; 7.883 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.349     ; 3.273      ;
; 7.883 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.349     ; 3.273      ;
; 7.884 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.350     ; 3.271      ;
; 7.884 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.350     ; 3.271      ;
; 7.884 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.350     ; 3.271      ;
; 7.886 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.344     ; 3.275      ;
; 7.888 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.350     ; 3.267      ;
; 7.898 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.378      ;
; 7.899 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 3.381      ;
; 7.899 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 3.381      ;
; 7.899 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 3.381      ;
; 7.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 3.378      ;
; 7.903 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.241     ; 3.372      ;
; 7.903 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.237     ; 3.376      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.243     ; 3.369      ;
; 7.920 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.229     ; 3.367      ;
; 7.920 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.229     ; 3.367      ;
; 7.920 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.229     ; 3.367      ;
; 7.921 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.230     ; 3.365      ;
; 7.921 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.230     ; 3.365      ;
; 7.921 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.230     ; 3.365      ;
; 7.923 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 3.369      ;
; 7.925 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.230     ; 3.361      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.478      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.478      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.478      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.478      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.478      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.478      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.478      ;
; 7.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.478      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.478      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.478      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.478      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.478      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.478      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.478      ;
; 7.969 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.478      ;
; 8.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 3.243      ;
; 8.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 3.243      ;
; 8.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 3.243      ;
; 8.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 3.243      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.070      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 3.064      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.069      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.190     ; 3.072      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.071      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.190     ; 3.072      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.071      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.190     ; 3.072      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.071      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.190     ; 3.072      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.071      ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 12.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 5.088      ;
; 12.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 5.088      ;
; 12.098 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 5.086      ;
; 12.098 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 5.086      ;
; 12.098 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 5.087      ;
; 12.098 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 5.087      ;
; 12.098 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 5.087      ;
; 12.098 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 5.087      ;
; 12.098 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 5.086      ;
; 12.098 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 5.086      ;
; 12.121 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.183     ; 5.032      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.193     ; 5.008      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.193     ; 5.008      ;
; 12.153 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.183     ; 5.000      ;
; 12.619 ; sdram_reset_n_reg ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.694      ;
; 12.621 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.149     ; 4.691      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.692      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.622 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 4.702      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
; 12.623 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.691      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.451 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 2.805      ;
; 2.451 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 2.805      ;
; 2.451 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 2.805      ;
; 2.451 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 2.805      ;
; 2.451 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 2.805      ;
; 2.451 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 2.805      ;
; 2.451 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 2.805      ;
; 2.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 2.805      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.141      ; 2.808      ;
; 2.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.815      ;
; 2.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.815      ;
; 2.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.815      ;
; 2.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.815      ;
; 2.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.147      ; 2.817      ;
; 2.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.815      ;
; 2.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.815      ;
; 2.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.815      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.142      ; 2.813      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.816      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.144      ; 2.815      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.816      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.144      ; 2.815      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.816      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.144      ; 2.815      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.145      ; 2.816      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.144      ; 2.815      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.144      ; 2.815      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.143      ; 2.814      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.456 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.137      ; 2.808      ;
; 2.457 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.136      ; 2.808      ;
; 2.457 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.136      ; 2.808      ;
; 2.457 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.136      ; 2.808      ;
; 2.457 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.136      ; 2.808      ;
; 2.457 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.136      ; 2.808      ;
; 2.669 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.154      ; 2.955      ;
; 2.669 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.154      ; 2.955      ;
; 2.669 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.154      ; 2.955      ;
; 2.669 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.154      ; 2.955      ;
; 2.812 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.140      ; 3.167      ;
; 2.812 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.140      ; 3.167      ;
; 2.812 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.140      ; 3.167      ;
; 2.812 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.140      ; 3.167      ;
; 2.812 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.140      ; 3.167      ;
; 2.812 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.140      ; 3.167      ;
; 2.812 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.140      ; 3.167      ;
; 2.813 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 3.167      ;
; 2.813 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 3.167      ;
; 2.813 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 3.167      ;
; 2.813 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 3.167      ;
; 2.813 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 3.167      ;
; 2.813 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 3.167      ;
; 2.813 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.139      ; 3.167      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.854 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.198      ; 4.268      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.256      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 4.257      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.258      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.258      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.258      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.258      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.258      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                          ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.321 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.730      ;
; 4.321 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.733      ;
; 4.321 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.729      ;
; 4.321 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.742      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.192      ; 4.729      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.731      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.731      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.731      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[17]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.731      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.733      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 4.730      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.731      ;
; 4.322 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.731      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[0]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[1]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[2]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[7]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[8]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[9]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[10]                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.737      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.736      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.736      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.736      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.736      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.736      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.736      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.736      ;
; 4.324 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.736      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.746      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.746      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.746      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.741      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_reset_reg                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.741      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 4.747      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serial_ip_framing_reg                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.741      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 4.747      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 4.747      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|allpot_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.741      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serial_ip_overrun_reg                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.741      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 4.747      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 4.747      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 4.748      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 4.747      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[1]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[2]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[3]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[4]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[5]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[6]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[7]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[8]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[9]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[10]                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[11]                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[12]                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[13]                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[14]                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[15]                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|en_delay_reg[16]                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 4.745      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 4.747      ;
; 4.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 4.747      ;
; 4.333 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.742      ;
; 4.333 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.190      ; 4.738      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.623 ; 5.778        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.624 ; 5.779        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.625 ; 5.780        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                               ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                          ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                          ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.071 ; 10.287       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit              ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6]             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]       ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]       ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[2]       ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1]         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed                ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110   ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.061 ; 17.443       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.080 ; 17.462       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]          ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]          ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]          ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]          ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ;
; 17.109 ; 17.325       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]             ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]             ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]             ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]             ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]       ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]       ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]       ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]       ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]       ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]           ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]           ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]            ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]            ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]      ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]      ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.110 ; 17.326       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]         ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]           ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]           ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]           ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]           ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]          ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]          ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]          ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]          ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]          ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ;
; 17.113 ; 17.329       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.437 ; 17.437       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.482 ; 17.482       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 89.470 ; 99.570       ; 10.100         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 90.316 ; 100.416      ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 99.570 ; 99.570       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                      ;
; 99.638 ; 99.638       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                        ;
; 99.646 ; 99.646       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                          ;
; 99.755 ; 99.939       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.755 ; 99.939       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.755 ; 99.939       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.755 ; 99.939       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.831 ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                     ;
; 99.831 ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                           ;
; 99.837 ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837 ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.842 ; 100.058      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.842 ; 100.058      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.842 ; 100.058      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.842 ; 100.058      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                   ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                   ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                   ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                    ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                          ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                          ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                           ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                          ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                          ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                            ;
; 99.914 ; 99.914       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                   ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.651 ; 2.758 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.649 ; 2.756 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.645 ; 2.752 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.642 ; 2.749 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.638 ; 2.745 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.627 ; 2.734 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 7.539 ; 8.299 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.079 ; 4.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 3.554 ; 3.909 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.189 ; 5.222 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 5.797 ; 5.696 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 7.539 ; 8.299 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.640 ; 7.459 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.908 ; 4.117 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 3.983 ; 4.289 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 5.766 ; 5.889 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 6.635 ; 6.627 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.640 ; 7.459 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 5.757 ; 5.982 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.731 ; 5.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.455 ; 3.769 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.728 ; 0.838 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 0.728 ; 0.838 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.767 ; -1.875 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.765 ; -1.873 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.761 ; -1.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.769 ; -1.877 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.757 ; -1.865 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.753 ; -1.861 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.542 ; -2.866 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.104 ; -3.427 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.542 ; -2.866 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -4.111 ; -4.124 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -4.753 ; -4.653 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.024 ; -3.219 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.694 ; -2.983 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.936 ; -3.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.011 ; -3.302 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -4.639 ; -4.765 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -5.479 ; -5.427 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.694 ; -2.983 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -4.724 ; -4.944 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -4.703 ; -4.864 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.505 ; -2.801 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326 ; 3.090 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336 ; 3.100 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325 ; 3.089 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637 ; 4.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633 ; 4.185 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507 ; 3.264 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519 ; 3.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639 ; 3.382 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623 ; 3.366 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648 ; 4.200 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614 ; 3.357 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624 ; 3.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.291 ; 4.765 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.439 ; 3.864 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.291 ; 4.765 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 8.224 ; 8.181 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 5.318 ; 4.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.754 ; 3.463 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.967 ; 7.103 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.847 ; 4.179 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.378 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 9.107 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.808 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.589 ; 2.539 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.371 ; 5.719 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.516 ; 2.399 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.255 ; 5.548 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.484 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.494 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.486 ; 2.369 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.495 ; 2.378 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.559 ; 2.327 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.578 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.588 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.859 ; 3.410 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.920 ; 3.473 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.917 ; 3.470 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.749 ; 2.510 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.760 ; 2.521 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.880 ; 2.627 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.940 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.864 ; 2.611 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.931 ; 3.484 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.855 ; 2.602 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.865 ; 2.612 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.676 ; 3.091 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.676 ; 3.091 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.495 ; 3.956 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.587 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.398 ; 7.372 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.506 ; 4.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.992 ; 2.708 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.186 ; 6.329 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.076 ; 3.399 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.700 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.434 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.872 ; 1.823 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.089 ; 2.060 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.664 ; 5.013 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.872 ; 1.823 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.654 ; 5.003 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.547 ; 4.841 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.796 ; 1.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.536 ; 4.830 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.765 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.765 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.775 ; 1.659 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.776 ; 1.660 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.766 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.775 ; 1.659 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.716 ; 2.716 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.716 ; 2.716 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.716 ; 2.716 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.716 ; 2.716 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.071 ; 3.071 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.729 ; 2.729 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.085 ; 3.085 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.095 ; 3.095 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.106 ; 3.106 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.171 ; 4.171 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.869 ; 3.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.504 ; 3.504 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.504 ; 3.504 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.494 ; 3.494 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.141 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.131 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.141 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.008 ; 3.632 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.774 ; 6.398 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 6.774 ; 6.398 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.681 ; 1.681 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.681 ; 1.681 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.681 ; 1.681 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.681 ; 1.681 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.023 ; 2.023 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.695 ; 1.695 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.036 ; 2.036 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.046 ; 2.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.057 ; 2.057 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.079 ; 3.079 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.790 ; 2.790 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.439 ; 2.439 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.439 ; 2.439 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.429 ; 2.429 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.090 ; 2.090 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.080 ; 2.080 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.090 ; 2.090 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.139 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.106 ; 5.745 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 6.106 ; 5.745 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.608     ; 2.679     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.608     ; 2.679     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.608     ; 2.679     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.608     ; 2.679     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.870     ; 2.941     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.621     ; 2.692     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.910     ; 2.981     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.953     ; 3.024     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.964     ; 3.035     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.918     ; 3.989     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.654     ; 3.725     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.317     ; 3.388     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.317     ; 3.388     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.307     ; 3.378     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.005     ; 3.076     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.995     ; 3.066     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.005     ; 3.076     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.463     ; 3.839     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.120     ; 6.496     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 6.120     ; 6.496     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.646     ; 1.782     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.646     ; 1.782     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.646     ; 1.782     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.646     ; 1.782     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.898     ; 2.034     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.659     ; 1.795     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.936     ; 2.072     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.978     ; 2.114     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.989     ; 2.125     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.905     ; 3.041     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.651     ; 2.787     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.327     ; 2.463     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.327     ; 2.463     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.317     ; 2.453     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.028     ; 2.164     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.018     ; 2.154     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.028     ; 2.164     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.616     ; 2.977     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.478     ; 5.839     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 5.478     ; 5.839     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                      ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -1.644 ; -63.903       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; -0.016 ; -0.073        ;
; FPGA_CLK                                                                       ; 1.612  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.726  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 13.876 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                       ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; -1.093 ; -42.076       ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.170  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.187  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.188  ; 0.000         ;
; FPGA_CLK                                                                       ; 0.194  ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                   ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.065  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.744  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14.713 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                   ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.220 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.912 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.147 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                        ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.605  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.476  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10.162 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.206 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.437 ; 0.000         ;
; FPGA_CLK                                                                       ; 89.472 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; -1.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.225     ; 0.449      ;
; -1.643 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.225     ; 0.448      ;
; -1.571 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.055     ; 0.546      ;
; -1.568 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.040     ; 0.558      ;
; -1.510 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.055     ; 0.485      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.055     ; 0.477      ;
; -1.496 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.487      ;
; -1.496 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.487      ;
; -1.494 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.485      ;
; -1.492 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.040     ; 0.482      ;
; -1.488 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.460      ;
; -1.485 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.457      ;
; -1.485 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.476      ;
; -1.482 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.473      ;
; -1.480 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.040     ; 0.470      ;
; -1.470 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.461      ;
; -1.470 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.461      ;
; -1.465 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.036     ; 0.459      ;
; -1.464 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.036     ; 0.458      ;
; -1.459 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.035     ; 0.454      ;
; -1.452 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.036     ; 0.446      ;
; -1.450 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.036     ; 0.444      ;
; -1.426 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.398      ;
; -1.416 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.061     ; 0.385      ;
; -1.415 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.387      ;
; -1.412 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.384      ;
; -1.411 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.383      ;
; -1.411 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.383      ;
; -1.410 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.056     ; 0.384      ;
; -1.408 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.053     ; 0.385      ;
; -1.406 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.053     ; 0.383      ;
; -1.400 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.042     ; 0.388      ;
; -1.399 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.371      ;
; -1.399 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.058     ; 0.371      ;
; -1.396 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.387      ;
; -1.395 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.386      ;
; -1.395 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.386      ;
; -1.394 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.053     ; 0.371      ;
; -1.393 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.036     ; 0.387      ;
; -1.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.383      ;
; -1.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.383      ;
; -1.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.039     ; 0.383      ;
; -1.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.036     ; 0.386      ;
; -1.383 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.193        ; -1.042     ; 0.371      ;
; 7.533  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[6]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 4.021      ;
; 7.533  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[3]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 4.021      ;
; 7.533  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[0]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 4.021      ;
; 7.546  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[2]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 4.010      ;
; 7.548  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[5]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 4.006      ;
; 7.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 3.929      ;
; 7.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 3.929      ;
; 7.686  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[6]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 3.873      ;
; 7.689  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[4]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.861      ;
; 7.689  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[1]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.861      ;
; 7.689  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot0_reg[7]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.861      ;
; 7.695  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 3.851      ;
; 7.695  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 3.851      ;
; 7.695  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 3.851      ;
; 7.695  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 3.851      ;
; 7.695  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 3.851      ;
; 7.695  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 3.851      ;
; 7.739  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[0]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.811      ;
; 7.739  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[1]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.811      ;
; 7.739  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[2]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.811      ;
; 7.739  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[3]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.811      ;
; 7.739  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[4]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.811      ;
; 7.739  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[5]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.811      ;
; 7.739  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[6]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.811      ;
; 7.739  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_counter_reg[7]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 3.811      ;
; 7.755  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.784      ;
; 7.759  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.075     ; 3.793      ;
; 7.759  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.075     ; 3.793      ;
; 7.764  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 3.784      ;
; 7.764  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[1]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 3.784      ;
; 7.764  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[2]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 3.784      ;
; 7.764  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 3.784      ;
; 7.764  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 3.784      ;
; 7.764  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 3.784      ;
; 7.764  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 3.784      ;
; 7.764  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 3.784      ;
; 7.778  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 3.760      ;
; 7.797  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 3.756      ;
; 7.797  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[1]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 3.756      ;
; 7.797  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[2]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 3.756      ;
; 7.797  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 3.756      ;
; 7.797  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 3.756      ;
; 7.797  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 3.756      ;
; 7.797  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 3.756      ;
; 7.797  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|count_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 3.756      ;
; 7.809  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 3.748      ;
; 7.809  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 3.748      ;
; 7.809  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 3.748      ;
; 7.809  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 3.748      ;
; 7.809  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 3.748      ;
; 7.809  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 3.748      ;
; 7.809  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 3.748      ;
; 7.809  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 3.748      ;
; 7.835  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.084     ; 3.708      ;
; 7.849  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.690      ;
; 7.856  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.083     ; 3.688      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                      ; To Node                                                                                                                                                                                                   ; Launch Clock                                                                   ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.016 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.640      ;
; -0.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.636      ;
; -0.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.636      ;
; -0.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.636      ;
; -0.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.634      ;
; -0.007 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.631      ;
; -0.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.628      ;
; 0.060  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.588      ; 0.556      ;
; 0.060  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.587      ; 0.555      ;
; 0.061  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.588      ; 0.555      ;
; 0.061  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.587      ; 0.554      ;
; 0.062  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.588      ; 0.554      ;
; 0.062  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.587      ; 0.553      ;
; 0.063  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.588      ; 0.553      ;
; 0.063  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.589      ; 0.554      ;
; 0.063  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.588      ; 0.553      ;
; 0.064  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.588      ; 0.552      ;
; 0.064  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.590      ; 0.554      ;
; 0.065  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.592      ; 0.555      ;
; 0.065  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.590      ; 0.553      ;
; 0.065  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.589      ; 0.552      ;
; 0.065  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.590      ; 0.553      ;
; 0.067  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.592      ; 0.553      ;
; 0.068  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.592      ; 0.552      ;
; 0.068  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.592      ; 0.552      ;
; 0.070  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.586      ; 0.544      ;
; 0.071  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.553      ;
; 0.071  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.553      ;
; 0.072  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.552      ;
; 0.072  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.552      ;
; 0.073  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.551      ;
; 0.073  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.598      ; 0.553      ;
; 0.075  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.596      ; 0.549      ;
; 0.075  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.590      ; 0.543      ;
; 0.076  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.592      ; 0.544      ;
; 0.076  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.590      ; 0.542      ;
; 0.083  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.590      ; 0.535      ;
; 0.100  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.592      ; 0.520      ;
; 0.168  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.592      ; 0.452      ;
; 0.170  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.201        ; 0.592      ; 0.450      ;
; 17.351 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.438      ;
; 17.357 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.228     ; 3.235      ;
; 17.360 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.429      ;
; 17.361 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.428      ;
; 17.366 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.423      ;
; 17.366 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.228     ; 3.226      ;
; 17.370 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.419      ;
; 17.372 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.417      ;
; 17.375 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.414      ;
; 17.378 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.228     ; 3.214      ;
; 17.382 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.407      ;
; 17.387 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.402      ;
; 17.407 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.382      ;
; 17.416 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.373      ;
; 17.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.361      ;
; 17.470 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.319      ;
; 17.479 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.310      ;
; 17.491 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.298      ;
; 17.538 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.030     ; 3.252      ;
; 17.547 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.030     ; 3.243      ;
; 17.559 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.030     ; 3.231      ;
; 17.618 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.171      ;
; 17.627 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.162      ;
; 17.639 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 3.150      ;
; 17.682 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.045     ; 3.046      ;
; 17.800 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 2.983      ;
; 17.815 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.045     ; 2.913      ;
; 17.845 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.045     ; 2.883      ;
; 17.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.046     ; 2.828      ;
; 17.928 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 2.861      ;
; 17.937 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 2.852      ;
; 17.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 2.840      ;
; 17.983 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.045     ; 2.745      ;
; 18.025 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.763      ;
; 18.033 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.046     ; 2.694      ;
; 18.034 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.754      ;
; 18.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 2.754      ;
; 18.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 2.746      ;
; 18.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 2.740      ;
; 18.044 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 2.745      ;
; 18.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.742      ;
; 18.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.736      ;
; 18.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.736      ;
; 18.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.736      ;
; 18.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.736      ;
; 18.056 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.031     ; 2.733      ;
; 18.057 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 2.727      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.039     ; 2.720      ;
; 18.077 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.049     ; 2.647      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                          ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 1.612   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 3.200        ; 1.735      ; 3.190      ;
; 97.287  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 100.000      ; -0.669     ; 2.031      ;
; 99.109  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                       ; FPGA_CLK    ; 100.000      ; 0.578      ; 0.338      ;
; 198.374 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.581      ;
; 198.378 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.577      ;
; 198.442 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.513      ;
; 198.443 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.512      ;
; 198.446 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.509      ;
; 198.447 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.508      ;
; 198.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.498      ;
; 198.494 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.461      ;
; 198.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.445      ;
; 198.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.444      ;
; 198.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.444      ;
; 198.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.441      ;
; 198.515 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.440      ;
; 198.515 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.440      ;
; 198.525 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.430      ;
; 198.525 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.430      ;
; 198.561 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.394      ;
; 198.562 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.393      ;
; 198.571 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.384      ;
; 198.575 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.380      ;
; 198.578 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.377      ;
; 198.579 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.376      ;
; 198.579 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.376      ;
; 198.582 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.373      ;
; 198.583 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.372      ;
; 198.583 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.372      ;
; 198.593 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.362      ;
; 198.593 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.362      ;
; 198.593 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.362      ;
; 198.628 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.327      ;
; 198.629 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.326      ;
; 198.630 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.325      ;
; 198.639 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.316      ;
; 198.643 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.312      ;
; 198.646 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.309      ;
; 198.647 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.308      ;
; 198.647 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.308      ;
; 198.647 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.308      ;
; 198.650 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.305      ;
; 198.651 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.304      ;
; 198.651 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.304      ;
; 198.651 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.304      ;
; 198.661 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.294      ;
; 198.661 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.294      ;
; 198.661 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.294      ;
; 198.661 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.294      ;
; 198.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.259      ;
; 198.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.258      ;
; 198.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.257      ;
; 198.699 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.256      ;
; 198.707 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.248      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.244      ;
; 198.714 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.241      ;
; 198.714 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.241      ;
; 198.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.240      ;
; 198.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.240      ;
; 198.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.240      ;
; 198.718 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.237      ;
; 198.718 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.237      ;
; 198.719 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.236      ;
; 198.719 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.236      ;
; 198.719 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.236      ;
; 198.729 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.226      ;
; 198.729 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.226      ;
; 198.729 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.226      ;
; 198.729 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.226      ;
; 198.730 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.225      ;
; 198.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.191      ;
; 198.765 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.190      ;
; 198.766 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.189      ;
; 198.766 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.189      ;
; 198.767 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.188      ;
; 198.775 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.180      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.176      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.172      ;
; 198.782 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.173      ;
; 198.782 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.173      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.169      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.172      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.172      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.172      ;
; 198.784 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.168      ;
; 198.786 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.169      ;
; 198.787 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.168      ;
; 198.787 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.168      ;
; 198.787 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.168      ;
; 198.797 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.158      ;
; 198.797 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.158      ;
; 198.797 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.158      ;
; 198.797 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.158      ;
; 198.798 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.157      ;
; 198.798 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.157      ;
; 198.832 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.123      ;
; 198.833 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.122      ;
; 198.834 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.121      ;
; 198.834 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.121      ;
; 198.834 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                       ; FPGA_CLK    ; 200.000      ; -0.032     ; 1.121      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                              ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.726 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.914      ;
; 3.758 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.882      ;
; 3.779 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 1.862      ;
; 3.796 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.115     ; 1.849      ;
; 3.811 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 1.830      ;
; 3.820 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.812      ;
; 3.833 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.807      ;
; 3.834 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.800      ;
; 3.852 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.786      ;
; 3.852 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.786      ;
; 3.852 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.780      ;
; 3.865 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.775      ;
; 3.866 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.768      ;
; 3.873 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.118     ; 1.769      ;
; 3.873 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.766      ;
; 3.877 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.755      ;
; 3.877 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.755      ;
; 3.877 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.755      ;
; 3.877 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.755      ;
; 3.884 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.754      ;
; 3.884 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.754      ;
; 3.905 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.734      ;
; 3.909 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.723      ;
; 3.909 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.723      ;
; 3.909 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.723      ;
; 3.909 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.723      ;
; 3.948 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.117     ; 1.695      ;
; 4.007 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 1.634      ;
; 4.035 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.652      ;
; 4.047 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 1.589      ;
; 4.050 ; SDRAM_ADDR[7]           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.583      ;
; 4.060 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.626      ;
; 4.060 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.626      ;
; 4.062 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 1.626      ;
; 4.068 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 1.620      ;
; 4.072 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 1.616      ;
; 4.091 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.595      ;
; 4.091 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.595      ;
; 4.093 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.541      ;
; 4.094 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.593      ;
; 4.094 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.593      ;
; 4.096 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.591      ;
; 4.097 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.583      ;
; 4.097 ; SDRAM_READ_ENABLE       ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.583      ;
; 4.098 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 1.590      ;
; 4.105 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.582      ;
; 4.116 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.523      ;
; 4.119 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.521      ;
; 4.125 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.509      ;
; 4.130 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.556      ;
; 4.140 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.546      ;
; 4.152 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.534      ;
; 4.156 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.476      ;
; 4.182 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.450      ;
; 4.188 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.444      ;
; 4.211 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.135     ; 1.414      ;
; 4.273 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.359      ;
; 4.310 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.324      ;
; 4.318 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.315      ;
; 4.333 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.344      ;
; 4.333 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.297      ;
; 4.334 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.343      ;
; 4.339 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.343      ;
; 4.339 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.343      ;
; 4.339 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.343      ;
; 4.339 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.343      ;
; 4.339 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.343      ;
; 4.339 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.343      ;
; 4.339 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.343      ;
; 4.348 ; SDRAM_ADDR[0]           ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 1.330      ;
; 4.353 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.282      ;
; 4.389 ; SDRAM_ADDR[0]           ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 1.289      ;
; 4.395 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.235      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.396 ; SDRAM_READ_ENABLE       ; ram_do_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.290      ;
; 4.401 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.123     ; 1.283      ;
; 4.407 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.223      ;
; 4.432 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.253      ;
; 4.436 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.123     ; 1.248      ;
; 4.471 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.211      ;
; 4.471 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.211      ;
; 4.471 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.211      ;
; 4.471 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.211      ;
; 4.471 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.211      ;
; 4.471 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.211      ;
; 4.471 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.211      ;
; 4.471 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 1.211      ;
; 4.480 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 1.203      ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                 ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 13.876 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 3.476      ;
; 13.921 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 3.432      ;
; 13.986 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.062     ; 3.352      ;
; 13.986 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 3.366      ;
; 13.996 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 3.356      ;
; 14.043 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 3.285      ;
; 14.045 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 3.307      ;
; 14.092 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.062     ; 3.246      ;
; 14.093 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.051     ; 3.256      ;
; 14.131 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 3.223      ;
; 14.132 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 3.221      ;
; 14.157 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 3.190      ;
; 14.173 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 3.181      ;
; 14.180 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.066     ; 3.154      ;
; 14.184 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.062     ; 3.154      ;
; 14.201 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 3.146      ;
; 14.264 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 3.088      ;
; 14.264 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 3.088      ;
; 14.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.061     ; 3.073      ;
; 14.276 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.067     ; 3.057      ;
; 14.285 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 3.069      ;
; 14.292 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 3.061      ;
; 14.296 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 3.056      ;
; 14.301 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 3.053      ;
; 14.304 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.061     ; 3.035      ;
; 14.306 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 3.047      ;
; 14.307 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 3.021      ;
; 14.314 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_event_reg                                                                                           ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 3.044      ;
; 14.323 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 3.029      ;
; 14.324 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 3.004      ;
; 14.330 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[4]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 3.028      ;
; 14.335 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.062     ; 3.003      ;
; 14.337 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 3.016      ;
; 14.354 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.974      ;
; 14.365 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.988      ;
; 14.406 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.052     ; 2.942      ;
; 14.414 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.052     ; 2.934      ;
; 14.417 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.911      ;
; 14.427 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 2.925      ;
; 14.450 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.052     ; 2.898      ;
; 14.451 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.902      ;
; 14.455 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.061     ; 2.884      ;
; 14.478 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.875      ;
; 14.490 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 2.862      ;
; 14.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.062     ; 2.837      ;
; 14.520 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.803      ;
; 14.529 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.222     ; 2.696      ;
; 14.533 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.820      ;
; 14.545 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.783      ;
; 14.564 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.789      ;
; 14.565 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.788      ;
; 14.620 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.222     ; 2.605      ;
; 14.622 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.731      ;
; 14.623 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.730      ;
; 14.631 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.222     ; 2.594      ;
; 14.651 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.672      ;
; 14.657 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.061     ; 2.682      ;
; 14.664 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.689      ;
; 14.668 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.685      ;
; 14.671 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.224     ; 2.552      ;
; 14.672 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.222     ; 2.553      ;
; 14.678 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[1]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 2.680      ;
; 14.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.630      ;
; 14.719 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 2.635      ;
; 14.740 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.224     ; 2.483      ;
; 14.751 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.224     ; 2.472      ;
; 14.765 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.588      ;
; 14.768 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.560      ;
; 14.768 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.585      ;
; 14.791 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 2.563      ;
; 14.793 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.560      ;
; 14.809 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.052     ; 2.539      ;
; 14.813 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.515      ;
; 14.814 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.224     ; 2.409      ;
; 14.815 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                                                                                                                      ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 2.546      ;
; 14.821 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[8]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.088     ; 2.538      ;
; 14.825 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.061     ; 2.514      ;
; 14.836 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[7]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.088     ; 2.523      ;
; 14.837 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.516      ;
; 14.841 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.487      ;
; 14.877 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[6]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 2.479      ;
; 14.898 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                                                                                                                      ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.462      ;
; 14.927 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[5]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 2.429      ;
; 14.933 ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                                                                                                     ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.427      ;
; 14.934 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 2.418      ;
; 14.934 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 2.418      ;
; 14.942 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[2]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.088     ; 2.417      ;
; 14.973 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.215     ; 2.259      ;
; 15.006 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.048     ; 2.346      ;
; 15.021 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.062     ; 2.317      ;
; 15.033 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 2.321      ;
; 15.034 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.047     ; 2.319      ;
; 15.073 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.217     ; 2.157      ;
; 15.075 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 2.279      ;
; 15.083 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.218     ; 2.146      ;
; 15.095 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.051     ; 2.254      ;
; 15.113 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[3]                                                                                        ; scanlines_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 2.243      ;
; 15.124 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 2.230      ;
; 15.143 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.215     ; 2.089      ;
; 15.144 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.046     ; 2.210      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                   ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.093 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.230      ; 0.399      ;
; -1.093 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.230      ; 0.399      ;
; -1.078 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.418      ;
; -1.077 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.231      ; 0.416      ;
; -1.074 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.422      ;
; -1.074 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.227      ; 0.415      ;
; -1.073 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.227      ; 0.416      ;
; -1.072 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.224      ; 0.414      ;
; -1.072 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.236      ; 0.426      ;
; -1.071 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.425      ;
; -1.070 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.426      ;
; -1.069 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.427      ;
; -1.069 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.427      ;
; -1.068 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.231      ; 0.425      ;
; -1.068 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.231      ; 0.425      ;
; -1.065 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.230      ; 0.427      ;
; -1.065 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.231      ; 0.428      ;
; -1.064 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.227      ; 0.425      ;
; -1.064 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.227      ; 0.425      ;
; -1.064 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.227      ; 0.425      ;
; -1.064 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.227      ; 0.425      ;
; -1.062 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.227      ; 0.427      ;
; -1.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.225      ; 0.426      ;
; -1.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.226      ; 0.427      ;
; -1.060 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.226      ; 0.428      ;
; -1.060 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.225      ; 0.427      ;
; -1.060 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.225      ; 0.427      ;
; -1.059 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.225      ; 0.428      ;
; -1.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.224      ; 0.447      ;
; -1.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.224      ; 0.449      ;
; -1.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.224      ; 0.449      ;
; -1.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.227      ; 0.454      ;
; -1.034 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.230      ; 0.458      ;
; -1.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.490      ;
; -1.005 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.491      ;
; -1.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.492      ;
; -1.002 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.494      ;
; -0.997 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.499      ;
; -0.997 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.499      ;
; -0.953 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.008        ; 1.234      ; 0.543      ;
; 0.185  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.507      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1111      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1111                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.214      ; 0.488      ;
; 0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.214      ; 0.491      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.214      ; 0.495      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[5]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[5]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[6]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[6]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[0]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[0]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[1]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[1]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[2]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[2]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[4]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[4]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[5]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[5]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[6]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[6]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[1]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[1]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[4]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[4]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[7]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[7]                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[0]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[0]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[2]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[2]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[1]                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[1]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_decode                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_decode                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                                                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                                                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serout_clock_reg                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serout_clock_reg                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                          ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; scanlines_reg                                                                                   ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.307      ;
; 0.192 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.312      ;
; 0.192 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.312      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.316      ;
; 0.200 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.320      ;
; 0.201 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.321      ;
; 0.210 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.330      ;
; 0.260 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.380      ;
; 0.260 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.380      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.382      ;
; 0.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.189 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.307      ;
; 0.189 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.307      ;
; 0.189 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.307      ;
; 0.189 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.307      ;
; 0.189 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.307      ;
; 0.196 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.314      ;
; 0.196 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.314      ;
; 0.196 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.314      ;
; 0.196 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.314      ;
; 0.196 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.315      ;
; 0.208 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.326      ;
; 0.226 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.345      ;
; 0.265 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.384      ;
; 0.275 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.393      ;
; 0.278 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.397      ;
; 0.278 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.396      ;
; 0.279 ; seq_reg[10]                                               ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.398      ;
; 0.282 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.401      ;
; 0.283 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.401      ;
; 0.289 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.408      ;
; 0.294 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.413      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.414      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.414      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.415      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.415      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.415      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.415      ;
; 0.298 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.416      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.302 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.420      ;
; 0.305 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.423      ;
; 0.310 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.428      ;
; 0.328 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.447      ;
; 0.353 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.472      ;
; 0.372 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.490      ;
; 0.402 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.520      ;
; 0.409 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.527      ;
; 0.409 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.528      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.532      ;
; 0.415 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.534      ;
; 0.423 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.541      ;
; 0.444 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.562      ;
; 0.445 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.563      ;
; 0.446 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.564      ;
; 0.446 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.564      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.572      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.572      ;
; 0.455 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.573      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.574      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.575      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.575      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.576      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.576      ;
; 0.459 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.577      ;
; 0.461 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.579      ;
; 0.463 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.582      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.027      ; 0.578      ;
; 0.497 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.616      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.625      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.625      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.626      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.627      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.628      ;
; 0.511 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.629      ;
; 0.512 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.630      ;
; 0.514 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.641      ;
; 0.515 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.635      ;
; 0.517 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.640      ;
; 0.519 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.636      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.638      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.638      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.639      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.641      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.641      ;
; 0.524 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.641      ;
; 0.524 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.642      ;
; 0.524 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.642      ;
; 0.527 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.645      ;
; 0.551 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.672      ;
; 0.553 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.676      ;
; 0.553 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.675      ;
; 0.556 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.675      ;
; 0.557 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.679      ;
; 0.560 ; seq_reg[9]                                                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.687      ;
; 0.560 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.687      ;
; 0.567 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.689      ;
; 0.573 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.027      ; 0.684      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                       ; To Node                                                                         ; Launch Clock                                                                   ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.194 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.313      ;
; 0.195 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.314      ;
; 0.199 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.318      ;
; 0.298 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.301 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.302 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.421      ;
; 0.306 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.425      ;
; 0.307 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.426      ;
; 0.307 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.426      ;
; 0.307 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.426      ;
; 0.308 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.427      ;
; 0.308 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.427      ;
; 0.312 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.431      ;
; 0.351 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.040        ; 2.173      ; 2.748      ;
; 0.447 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.449 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.454 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.576      ;
; 0.455 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.574      ;
; 0.456 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.575      ;
; 0.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.579      ;
; 0.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.462 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.462 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.463 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.582      ;
; 0.465 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.584      ;
; 0.466 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.585      ;
; 0.468 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.587      ;
; 0.469 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.588      ;
; 0.508 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.630      ;
; 0.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.629      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.633      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.513 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.515 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.518 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.637      ;
; 0.519 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.638      ;
; 0.519 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.638      ;
; 0.520 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.639      ;
; 0.520 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.642      ;
; 0.520 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.642      ;
; 0.521 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.640      ;
; 0.522 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.641      ;
; 0.522 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.641      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.642      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.645      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.642      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.645      ;
; 0.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.525 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.525 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.526 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.645      ;
; 0.526 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.645      ;
; 0.527 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.646      ;
; 0.527 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                       ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.646      ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                         ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.485      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.485      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 2.488      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[30]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.481      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.075     ; 2.487      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[27]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 2.488      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[27]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 2.488      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.078     ; 2.484      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[30]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 2.488      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.485      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|clock_reg                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 2.488      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|clock_sync_reg                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 2.488      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[2]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.069     ; 2.493      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.485      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.074     ; 2.488      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[5]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[6]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.073     ; 2.489      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[3]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|syncreset_enable_divider:enable_64_div|enabled_out_reg                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.071     ; 2.491      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.070     ; 2.492      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.485      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.485      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_clock_reg                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.485      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.068     ; 2.494      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.485      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
; 9.065 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.486      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.135     ; 1.701      ;
; 9.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.135     ; 1.701      ;
; 9.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.135     ; 1.701      ;
; 9.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.137     ; 1.699      ;
; 9.745 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.136     ; 1.699      ;
; 9.746 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 1.641      ;
; 9.746 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 1.643      ;
; 9.746 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 1.643      ;
; 9.746 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 1.643      ;
; 9.747 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.190     ; 1.641      ;
; 9.747 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.136     ; 1.697      ;
; 9.748 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.140     ; 1.692      ;
; 9.749 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.190     ; 1.639      ;
; 9.749 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.142     ; 1.689      ;
; 9.750 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 1.634      ;
; 9.751 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 1.631      ;
; 9.754 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.134     ; 1.692      ;
; 9.754 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.134     ; 1.692      ;
; 9.754 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.134     ; 1.692      ;
; 9.754 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.714      ;
; 9.754 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.714      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.713      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.713      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.713      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.713      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.715      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 1.634      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 1.634      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 1.634      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.132     ; 1.692      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.132     ; 1.692      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.132     ; 1.692      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 1.634      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 1.634      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 1.634      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.128     ; 1.693      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.134     ; 1.687      ;
; 9.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 1.635      ;
; 9.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 1.629      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.707      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 1.706      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 1.706      ;
; 9.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 1.708      ;
; 9.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 1.707      ;
; 9.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 1.707      ;
; 9.789 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.729      ;
; 9.789 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.729      ;
; 9.789 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.729      ;
; 9.789 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.729      ;
; 9.789 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.729      ;
; 9.789 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.729      ;
; 9.789 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.729      ;
; 9.790 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.728      ;
; 9.790 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.728      ;
; 9.790 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.728      ;
; 9.790 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.728      ;
; 9.790 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.728      ;
; 9.790 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.728      ;
; 9.790 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.728      ;
; 9.790 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.728      ;
; 9.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.598      ;
; 9.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.598      ;
; 9.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.598      ;
; 9.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.598      ;
; 9.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.540      ;
; 9.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.540      ;
; 9.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.540      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.532      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.532      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.532      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 1.540      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 1.540      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.532      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 1.539      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 1.532      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 1.540      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 1.538      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 1.541      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 1.541      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 1.541      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 1.541      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.542      ;
; 9.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 1.540      ;
; 9.984 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 1.532      ;
; 9.984 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 1.532      ;
; 9.984 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 1.532      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 14.713 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 2.588      ;
; 14.716 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.110     ; 2.574      ;
; 14.716 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.110     ; 2.574      ;
; 14.730 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 2.570      ;
; 14.735 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 2.579      ;
; 14.735 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 2.580      ;
; 14.735 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 2.580      ;
; 14.735 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 2.580      ;
; 14.735 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 2.580      ;
; 14.735 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.581      ;
; 14.735 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.581      ;
; 14.736 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 2.578      ;
; 14.736 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 2.578      ;
; 14.736 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 2.578      ;
; 14.956 ; sdram_reset_n_reg ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.412      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.418      ;
; 14.961 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.417      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.410      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.411      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.411      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.411      ;
; 14.964 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.072     ; 2.411      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.220 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.220 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.220 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.220 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.220 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.220 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.220 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.220 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.221 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.397      ;
; 1.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.397      ;
; 1.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.397      ;
; 1.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.397      ;
; 1.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.397      ;
; 1.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.397      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.222 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.398      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.397      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.397      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.397      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.405      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.405      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.397      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.404      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.397      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.405      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.403      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.406      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.403      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.406      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.403      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.403      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.403      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.406      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.403      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.406      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.403      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.403      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.407      ;
; 1.225 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.405      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.405      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.405      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.405      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.405      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.405      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.405      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.398      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.405      ;
; 1.226 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.405      ;
; 1.313 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.465      ;
; 1.313 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.465      ;
; 1.313 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.465      ;
; 1.313 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.465      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.570      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.571      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.571      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.571      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.571      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.570      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.570      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.571      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.570      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.570      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.571      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.570      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.570      ;
; 1.396 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.571      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.109      ; 2.125      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.108      ; 2.124      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.107      ; 2.123      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.107      ; 2.123      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.107      ; 2.123      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.107      ; 2.123      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.107      ; 2.123      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.107      ; 2.123      ;
; 1.912 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.107      ; 2.123      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.112      ; 2.129      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
; 1.913 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.113      ; 2.130      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                          ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.147 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.358      ;
; 2.147 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.363      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.358      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[0]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.111      ; 2.363      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[1]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.111      ; 2.363      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[2]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.111      ; 2.363      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[3]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.364      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[4]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.364      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[5]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.364      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[6]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.364      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[7]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.111      ; 2.363      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[8]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.111      ; 2.363      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[9]                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.111      ; 2.363      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|subtimer_reg[10]                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.111      ; 2.363      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.362      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.362      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.362      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.362      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.362      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.362      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.362      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.362      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[17]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.359      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.360      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.148 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.357      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.360      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.358      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.357      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.360      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.357      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.357      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.357      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.357      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.357      ;
; 2.149 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.357      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.365      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[5]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.366      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[16]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.367      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[16]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.367      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.367      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.368      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.365      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[26]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.369      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[2]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.111      ; 2.371      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.372      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.372      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.372      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.372      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.372      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.372      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.372      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.112      ; 2.372      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
; 2.156 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.110      ; 2.370      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.608 ; 5.763        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.609 ; 5.764        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.609 ; 5.764        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                              ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg       ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg       ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0  ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0  ;
; 8.479 ; 8.709        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.479 ; 8.709        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.479 ; 8.709        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.479 ; 8.709        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.481 ; 8.711        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.481 ; 8.711        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126]                                                                                ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]                                                                                  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]                                                                                  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]                                                                                  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                 ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 10.196 ; 10.380       ; 0.184          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[2]                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate                                    ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]                                              ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_address_reg0       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_we_reg             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                      ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                        ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                             ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                             ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                             ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                             ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                      ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                        ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_datain_reg0        ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                             ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                             ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                 ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                   ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                 ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                   ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[0]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[10]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[12]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[13]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[14]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[16]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[17]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[18]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[19]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[1]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[20]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[21]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[22]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[2]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[3]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[4]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[5]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[6]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[7]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[8]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[9]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[10]                                                                                                                                                                                                                                     ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[12]                                                                                                                                                                                                                                     ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[13]                                                                                                                                                                                                                                     ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[14]                                                                                                                                                                                                                                     ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[15]                                                                                                                                                                                                                                     ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[16]                                                                                                                                                                                                                                     ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[17]                                                                                                                                                                                                                                     ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[18]                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.451 ; 17.451       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.458 ; 17.458       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.458 ; 17.458       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.462 ; 17.462       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.462 ; 17.462       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.468 ; 17.468       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                         ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 89.472  ; 99.572       ; 10.100         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 90.322  ; 100.422      ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 99.263  ; 99.447       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.263  ; 99.447       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.263  ; 99.447       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.263  ; 99.447       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                     ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                           ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.442  ; 99.442       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                    ;
; 99.443  ; 99.443       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                   ;
; 99.443  ; 99.443       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                   ;
; 99.443  ; 99.443       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                   ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                           ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.452  ; 99.452       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                   ;
; 99.453  ; 99.453       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                          ;
; 99.453  ; 99.453       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                            ;
; 99.549  ; 99.549       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                        ;
; 99.554  ; 99.554       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                          ;
; 99.572  ; 99.572       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                      ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 100.335 ; 100.551      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.486 ; 2.044 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.491 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.489 ; 2.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.485 ; 2.043 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.483 ; 2.041 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.471 ; 2.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 4.111 ; 4.492 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 2.320 ; 2.774 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 1.990 ; 2.529 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 2.681 ; 3.230 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 2.951 ; 3.511 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 4.111 ; 4.492 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 3.733 ; 4.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 2.222 ; 2.684 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 2.253 ; 2.706 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 2.961 ; 3.534 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 3.280 ; 3.885 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 3.733 ; 4.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.155 ; 3.961 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 3.131 ; 3.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 1.984 ; 2.451 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.461 ; -1.992 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.804 ; -2.256 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.461 ; -1.992 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.124 ; -2.661 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.411 ; -2.964 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.675 ; -2.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.558 ; -2.063 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.712 ; -2.170 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.741 ; -2.191 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.387 ; -2.957 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.691 ; -3.265 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.558 ; -2.063 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.609 ; -3.405 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.585 ; -3.320 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.482 ; -1.945 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.596 ; 1.445 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.604 ; 1.453 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.613 ; 1.462 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.615 ; 1.464 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.625 ; 1.474 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.609 ; 1.458 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.594 ; 2.300 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.627 ; 2.349 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.622 ; 2.344 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.163 ; 1.075 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.685 ; 1.535 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.695 ; 1.545 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.764 ; 1.618 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.632 ; 2.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.756 ; 1.610 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.766 ; 1.620 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.164 ; 2.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.676 ; 1.657 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.164 ; 2.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.629 ; 1.478 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 4.114 ; 4.776 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 2.367 ; 2.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.609 ; 1.664 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.618 ; 4.175 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.886 ; 1.800 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.371 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.318 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 2.932 ; 3.400 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.316 ; 1.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.932 ; 3.400 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.137 ; 1.199 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.923 ; 3.391 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 2.885 ; 3.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.885 ; 3.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.108 ; 1.074 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.118 ; 1.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.108 ; 1.074 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.873 ; 3.306 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.099 ; 1.065 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.086 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.096 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.099 ; 1.065 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.089 ; 1.055 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.097 ; 1.063 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.257 ; 1.242 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.257 ; 1.242 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.725 ; 1.645 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.675 ; 4.330 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.933 ; 2.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.197 ; 1.248 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.196 ; 3.749 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.462 ; 1.380 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.998 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.944 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.741 ; 0.803 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.920 ; 0.939 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.537 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.741 ; 0.803 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.527 ; 2.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.488 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.721 ; 0.687 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.477 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.702 ; 0.668 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.075 ; 2.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.075 ; 2.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.075 ; 2.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.075 ; 2.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.218 ; 2.191 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.087 ; 2.060 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.244 ; 2.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.265 ; 2.238 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.276 ; 2.249 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.779 ; 2.752 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.633 ; 2.606 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.454 ; 2.427 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.454 ; 2.427 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.444 ; 2.417 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.287 ; 2.260 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.277 ; 2.250 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.287 ; 2.260 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.894 ; 2.518 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.270 ; 3.894 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 4.270 ; 3.894 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.778 ; 0.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.778 ; 0.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.778 ; 0.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.778 ; 0.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 0.915 ; 0.915 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 0.790 ; 0.790 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 0.940 ; 0.940 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 0.961 ; 0.961 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 0.971 ; 0.971 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.455 ; 1.455 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.314 ; 1.314 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.143 ; 1.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.143 ; 1.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.133 ; 1.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.982 ; 0.982 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.972 ; 0.972 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.982 ; 0.982 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.377 ; 2.016 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.871 ; 3.510 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 3.871 ; 3.510 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.132     ; 2.132     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.132     ; 2.132     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.132     ; 2.132     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.132     ; 2.132     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.296     ; 2.296     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.147     ; 2.147     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.319     ; 2.319     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.336     ; 2.336     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.347     ; 2.347     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.897     ; 2.897     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.741     ; 2.741     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.548     ; 2.548     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.548     ; 2.548     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.538     ; 2.538     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.367     ; 2.367     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.357     ; 2.357     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.367     ; 2.367     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.624     ; 3.000     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.091     ; 4.467     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 4.091     ; 4.467     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.832     ; 0.949     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.832     ; 0.949     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.832     ; 0.949     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.832     ; 0.949     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 0.991     ; 1.108     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 0.847     ; 0.964     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.012     ; 1.129     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.029     ; 1.146     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.040     ; 1.157     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.568     ; 1.685     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.418     ; 1.535     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.233     ; 1.350     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.233     ; 1.350     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.223     ; 1.340     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.058     ; 1.175     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.048     ; 1.165     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.058     ; 1.175     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.117     ; 2.478     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.699     ; 4.060     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 3.699     ; 4.060     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                             ;
+---------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+
; Clock                                                                           ; Setup    ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
+---------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+
; Worst-case Slack                                                                ; -3.539   ; -1.918  ; 5.996    ; 1.220   ; 5.518               ;
;  FPGA_CLK                                                                       ; -0.348   ; 0.194   ; N/A      ; N/A     ; 89.439              ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.070    ; 0.188   ; 7.513    ; 1.220   ; 5.518               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.539   ; 0.170   ; 5.996    ; 2.147   ; 17.028              ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 9.353    ; 0.187   ; 11.686   ; 1.912   ; 8.431               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A     ; N/A      ; N/A     ; 17.423              ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; -0.267   ; -1.918  ; N/A      ; N/A     ; 10.071              ;
; Design-wide TNS                                                                 ; -137.066 ; -73.383 ; 0.0      ; 0.0     ; 0.0                 ;
;  FPGA_CLK                                                                       ; -0.348   ; 0.000   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000    ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -134.978 ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000    ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A     ; N/A      ; N/A     ; 0.000               ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; -2.778   ; -73.383 ; N/A      ; N/A     ; 0.000               ;
+---------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026 ; 3.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 8.420 ; 8.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.654 ; 4.870 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.063 ; 4.343 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.751 ; 5.807 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 6.387 ; 6.337 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 8.420 ; 8.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 7.461 ; 8.050 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.440 ; 4.571 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.536 ; 4.728 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 6.396 ; 6.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 7.293 ; 7.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 7.461 ; 8.050 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.551 ; 6.900 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.526 ; 6.792 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.957 ; 4.166 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 0.864 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.461 ; -1.992 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.804 ; -2.256 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.461 ; -1.992 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.124 ; -2.661 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.411 ; -2.964 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.675 ; -2.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.558 ; -2.063 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.712 ; -2.170 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.741 ; -2.191 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.387 ; -2.957 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.691 ; -3.265 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.558 ; -2.063 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.609 ; -3.405 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.585 ; -3.320 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.482 ; -1.945 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326 ; 3.090 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336 ; 3.100 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325 ; 3.089 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637 ; 4.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633 ; 4.185 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507 ; 3.264 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519 ; 3.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639 ; 3.382 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623 ; 3.366 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648 ; 4.200 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614 ; 3.357 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624 ; 3.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.302 ; 4.765 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.439 ; 3.864 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.302 ; 4.765 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 8.224 ; 8.248 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 5.318 ; 5.015 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.754 ; 3.463 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.967 ; 7.103 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.847 ; 4.179 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.378 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 9.107 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.808 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.589 ; 2.539 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.371 ; 5.719 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.516 ; 2.399 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.255 ; 5.548 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.484 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.494 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.486 ; 2.369 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.495 ; 2.378 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.257 ; 1.242 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.257 ; 1.242 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.725 ; 1.645 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.675 ; 4.330 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.933 ; 2.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.197 ; 1.248 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.196 ; 3.749 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.462 ; 1.380 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.998 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.944 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.741 ; 0.803 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.920 ; 0.939 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.537 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.741 ; 0.803 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.527 ; 2.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.488 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.721 ; 0.687 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.477 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.702 ; 0.668 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_P         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; USB2_P       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; USB2_N       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                             ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 248      ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10206    ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 16671094 ; 0        ; 78841    ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 44       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 74       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1289     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                       ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                       ; FPGA_CLK                                                                       ; 352      ; 1        ; 1        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 40       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10028    ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 248      ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10206    ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 16671094 ; 0        ; 78841    ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 44       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 74       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1289     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                       ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                       ; FPGA_CLK                                                                       ; 352      ; 1        ; 1        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 40       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10028    ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                          ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 656      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2421     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 177      ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                           ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 656      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2421     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 177      ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 31    ; 31   ;
; Unconstrained Input Port Paths  ; 63    ; 63   ;
; Unconstrained Output Ports      ; 57    ; 57   ;
; Unconstrained Output Port Paths ; 76    ; 76   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Jan 16 03:52:38 2016
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 236.25 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 11 -multiply_by 63 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {usb_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 48 -duty_cycle 50.00 -name {usb_pll|altpll_component|auto_generated|pll1|clk[0]} {usb_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.539
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.539      -134.978 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.215        -0.215 FPGA_CLK 
    Info (332119):    -0.190        -1.873 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.070         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.353         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.918
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.918       -73.383 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.453         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.454         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.455         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.494         0.000 FPGA_CLK 
Info (332146): Worst-case recovery slack is 5.996
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.996         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.513         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.686         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 2.740
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.740         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.313         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     4.770         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.518
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.518         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.431         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.108         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.028         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.423         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.439         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.174
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.174      -119.089 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.348        -0.348 FPGA_CLK 
    Info (332119):    -0.267        -2.778 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.353         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.658         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.673
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.673       -63.841 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.404         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.458         0.000 FPGA_CLK 
Info (332146): Worst-case recovery slack is 6.421
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.421         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.854         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    12.097         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 2.451
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.451         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.854         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     4.321         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.519
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.519         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.431         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.071         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.061         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.426         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.470         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.644
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.644       -63.903 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.016        -0.073 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.612         0.000 FPGA_CLK 
    Info (332119):     3.726         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.876         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.093
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.093       -42.076 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.170         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.187         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.188         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.194         0.000 FPGA_CLK 
Info (332146): Worst-case recovery slack is 9.065
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     9.065         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.744         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.713         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 1.220
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.220         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.912         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     2.147         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.605
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.605         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.476         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.162         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.206         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.437         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.472         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 524 megabytes
    Info: Processing ended: Sat Jan 16 03:52:55 2016
    Info: Elapsed time: 00:00:17
    Info: Total CPU time (on all processors): 00:00:21


